28377X EMIF

Hi Abhijit,

Figure 24-9 in TRM clearly shows how to connect the address lines for 16bit memory. You need to connect EMxBA[1] to A0 of memory device and EMxA0 to A1 of memory device and so on.

Reference to address line EM1A[22] is not correct. We'll update the document accordingly.

Regards,

Vivek Singh

Hi.. Vivek ,

thanks for details.

I raise this question even after seeing that diagram for following reasons

1. the explanation in same point no.24.2.6.1. is

Therefore, when interfacing to a 16-bit or 8-bit asynchronous device, the EM1BA[1] and EM1BA[0] pins provide the least significant bits of the halfword or byte address, respectively.

which is again confusing.

2. For A0-A21 address space you have not specified half word side, upper or lower. Also, like SDRAM, no clear address mapping table is available. 

3. With EM1BA0 connected to A0 of memory total address space at memory side will be A0 to A22 so total memory size as per address lines will become (0x3DFFFF-0x300000=512K+384K=896K) on processor side and (0x7BFFFF - 0x60000 =0x1BFFFF=1792K) on memory side. which is again not clear. 

Above details do not give me clear picture, what size of SRAM memory chip will be required and how to connect it.

regards

Abhijit Kelkar

Hi.. Vivek,
In continuation to my earlier reply;
When I am using 16bit EMIF interface I thought it should be similar to 16 bit F28x interface as in the same manual, table 3.14 bottom note 1 clearly mention that,
- All 32-bit operations are done in little endian format (C28X is 16 bit addressable).
Example: a 32-bit IPC write is handles as below:
• Data[15:0] is written in address
• Data [31:16] is written in address+1
so I assume same add/data bus is connected to EMIF
I have also used F2812 external memory interface, where data interface is having same little endian format and there is no signal like BA0/BA1.
Sorry but I thought it will be useful input for you when U will be changing manual.
regards
Abhijit Kelkar

Abhijit,

Yes, it's littile endian format.

F2812 device had different module (XINTF) than one used on this device (EMIF)hence there are some differences in singals.

Let me know if you have any further queries on this.

Regards,

Vivek Singh

Vivek,

thanks ,

That means for 32 bit data, there will be two 16 bit read/ write cycles from CPU and for 16 bit data there will be only single. Based on global declaration, CCS will take care of it and it add additional read/write cycle for 32 bit data. Am I correct?  

Please answer my point no.2,3 from my first part for connecting BA[0] signal to A0 of corresponding 16 bit device and explain use of BA[0] for address formation.

Sorry I am troubling you but with such queries only you will re-write these preliminary editions to more clear versions.

thanks

Abhijit  

Abhijit,

Yes, if memory is 16bit then 32bit access from CPU will be split into two 16bit access by EMIF and send to external memory device. Not sure what do you mean by "CCS will take care of it". This is taken care in hardware (EMIF IP) itself. Are you referring to memory watch window here?

2. For A0-A21 address space you have not specified half word side, upper or lower. Also, like SDRAM, no clear address mapping table is available. 

A0-A21 is 32bit address. BA[1] is used for 16bit addressing and BA[0] is used for byte address.

3. With EM1BA0 connected to A0 of memory total address space at memory side will be A0 to A22 so total memory size as per address lines will become (0x3DFFFF-0x300000=512K+384K=896K) on processor side and (0x7BFFFF - 0x60000 =0x1BFFFF=1792K) on memory side. which is again not clear. 

For 16bit memory, you need to connect BA[1] to A0 of memory device not BA[0]. I don't understand the IInd part of the question. Connecting BA[0] or BA[1] to A0 of memory device doesn't change address map on CPU side. It's just the EMIF IP which manipulates the LSB of address based on the configuration of "ASIZE" bit field in ASYNC_CSx_CR register. Not sure what is the confusion here.

Regards,

Vivek Singh

Vivek,

1. My reference to CCS means that while compiling the program CCS will use 32 bit read/write related machine level command when I define 32 bit data automatically there will be 2 read/write operations

2. Yes I will be connecting BA[1] to A0 of memory. It was my typo error.

Now to explain my point3

As per memory map, combine address range for CS3 & CS4 is 0x30 0000 to 0x3D FFFF =896K

Physical it will require A0 to A21 address lines i.e. x=21

As per your dia. 24.9 of technical manual I have to make following connections

EM1BA[1] --> A[0] of memory 

EM1A[x:0]--> A[(x+1):1] of memory here x is 21 so my EM1A21 will be connected to A22 of memory

Accordingly required memory IC should also have address lines from A0-A22 i.e. required memory IC should be of 8192k capacity

I want to know if above statement is correct or not? and if I am not correct then let me know where is problem in my understanding.  

regards

Abhijit

Abhijit,

1. My reference to CCS means that while compiling the program CCS will use 32 bit read/write related machine level command when I define 32 bit data automatically there will be 2 read/write operations

Ok, you mean compiler. No, it's taken care in hardware (inside EMIF IP).

As per your dia. 24.9 of technical manual I have to make following connections

EM1BA[1] --> A[0] of memory 

EM1A[x:0]--> A[(x+1):1] of memory here x is 21 so my EM1A21 will be connected to A22 of memory

Accordingly required memory IC should also have address lines from A0-A22 i.e. required memory IC should be of 8192k capacity

I want to know if above statement is correct or not? and if I am not correct then let me know where is problem in my understanding.  

Your understanding is correct but it's not necessary to match the address lines on external memory device with what is available on device. If extrnal device has more address lines then you could tie the upper address lines to '0' and if it's less then you can leave the address lines from device unconnected.  Does this make sense?

Regards,

Vivek Singh

Vivek Singh,

thanks for reply.

So.. my understanding is correct. Then

1. Can u explain me use of EM1BA[1] in actual address generation. 

Say for CPU address of 0x310101 for EMIF(i.e. CS3 area) what is logic level of EM1BA[1] and what will be effective address generated on 16 bit device side with connection discussed earlier as per Fig. 24.9- B. Here I am assuming that logic levels of A0 to A21 pins will be corresponding to physical address 0x310101(=0011 0001 0000 0001 0000 0001 B) & will come as it is on external pins.

As I will be also connecting a FPGA IC with some integrated logic as well as I/O expansion, these addresses are not continuous so I have to understand address transformation with EM1BA[1]

2.   Yes U are right that I need not have to connect all address lines but adding EM1BA[1] to LSB side increase address lines by 1. For address range 0x30 0000 to 0x3d ffff, I can use EM1A20,EM1A21 with CS3 & CS4 in CS logic but lower address bits EM1BA[1], EM1A0 to EM1A19 will require one to one connection on memory side. So I will require memory with A0 to A20 address lines so effective address range @ memory side is 0x1f ffff. Now how physical CPU address range of 0xD FFFF(917503 physical 16 bit locations) is distributed in memory address range of 0x 1F FFFF (2097151 Physical 16 bit locations) i.e. for every CPU address there are at least 2 different addresses at memory side. This is my main concern.

Above point is not clearly explained in technical manual  & given details are not sufficient from Hardware design view point.  You need to show physical address mapping with use of BA[1]i.e. additional address line.

Hope U understand my requirement.

regards

Abhijit 

Hi Abhijit,

Sorry for late reply.

1. Can u explain me use of EM1BA[1] in actual address generation. 

Say for CPU address of 0x310101 for EMIF(i.e. CS3 area) what is logic level of EM1BA[1] and what will be effective address generated on 16 bit device side with connection discussed earlier as per Fig. 24.9- B. Here I am assuming that logic levels of A0 to A21 pins will be corresponding to physical address 0x310101(=0011 0001 0000 0001 0000 0001 B) & will come as it is on external pins.

EM1BA[1] is LSB of address so for address 0x310101 on CPU side, EM1BA[1] will be driven high ('1'). CPU address is mapped to (Ax..A0,EM1BA[1]) on EMIF side.

2.   Yes U are right that I need not have to connect all address lines but adding EM1BA[1] to LSB side increase address lines by 1. For address range 0x30 0000 to 0x3d ffff, I can use EM1A20,EM1A21 with CS3 & CS4 in CS logic but lower address bits EM1BA[1], EM1A0 to EM1A19 will require one to one connection on memory side. So I will require memory with A0 to A20 address lines so effective address range @ memory side is 0x1f ffff. Now how physical CPU address range of 0xD FFFF(917503 physical 16 bit locations) is distributed in memory address range of 0x 1F FFFF (2097151 Physical 16 bit locations) i.e. for every CPU address there are at least 2 different addresses at memory side. This is my main concern.

We have different signals and address map for CS3/CS4 so not sure why do you want to use extra address lines in CS logic. Look like I am still missing your application usecase. Do you have planned schematic which shows actual connection?

Regards,

Vivek Singh

Hi.. Vivek Singh ,

thanks for reply.

OK EM1BA[1] is clear.

I have tried to explain my confusion in different way, now let us work in other way.

Since you have different address maps for CS 3/4, can I request you to please give me CPU to 16 bit Memory connection diagram where I can to use full address range of 0x30 0000 to 0x3D FFFF.  But be sure to show each and every pin connection on Memory side and give me part no. of that memory.  I think that will solve my confusion.

My email address is aakelkar1@gmail.com 

regards

Abhijit kelkar 

Hi.. Vivek Singh,

Sorry this time I could not reply you immediately.

1. If EM1BA[1] is copy LSB of address 0x310101 i.e. EM1BA[1] =1 then what is bit status of EM1A0 to EM1A21. How address 0x310101 will be mapped on EM1A0 to EM1A21. Will EM1A[0] will again have LSB value of address i.e.'1' high?. What is effective address seen from SRAM connected to EMIF.

For your reference I have attached PDF file for 512Kx 16 bit ISSI SRAM can you  please let me to address/control pin connections for using full address range of CS3  or CS4. Probably that will solve my confusion Or else if you have any connection diagram for using full  address range of CS3 & CS4 please let me see it.

thanks

Abhijit Kelkar

  ISSI_512Kx16_SRAM.pdf