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SolarExplorer_PVInverter_F28M35x_C28x DPlibFlt Question

Hello everyone,

I currently working on a simple project whcih is control a boost converter using a voltage loop controller 3p3z.

I revise the SolarExplorer_PVInverter Project

I find out the PWMDRV_1ch.asm have the following issue

I replace the SolarExplorer_PVInverter Project's PWMDRV_1ch_UpDwnCntCompl code in main.c and SolarExplorer-DPL-ISR.asm.asm

and include the PWMDRV_1ch.c into the project.

BUT I suddenly encounter a error at the "PWMDRV_1ch.asm"

the error state that

"

Description Resource Path Location Type
[E9999] Pipeline write-read conflict detected Boost-DPL-ISR.asm /BoostTemplete line 91 C/C++ Problem

"

Is there anything I need to notice that I using the DPlibFlt Library?

I indeed follow the DPlibFlt Library PDF usage.

The following is the Boost-DPL-ISR.asm I write

::::::::::::::::::


;----------------------------------------------------------------------------------
; FILE: SolarExplorer-DPL-ISR.asm
;
; Description: SolarExplorer-DPL-ISR.asm contains the ISR for the system
;
;----------------------------------------------------------------------------------

;Gives peripheral addresses visibility in assembly
.cdecls C,LIST,"F28M35x_Device.h"

;include C header file - sets INCR_BUILD etc.(used in conditional builds)
.cdecls C,NOLIST, "Boost-Setting.h"

;Include files for the Power Library Maco's being used by the system

.include "PWMDRV_1ch_UpDwnCntCompl.asm"
.include "PWMDRV_1ch.asm"
.include "ADC1DRV_1ch.asm"
.include "ADC2DRV_1ch.asm"
.include "CNTL_2P2Z.asm"
.include "MATH_EMAVG.asm"
;=============================================================================
; Digital Power library - Initailization Routine
;=============================================================================
; dummy variable for pointer initialisation
ZeroNet .usect "ZeroNet_Section",2,1,1 ; output terminal 1

.text

; label to DP initialisation function
.def _DPL_Init
_DPL_Init:
ZAPA
MOVL XAR0, #ZeroNet
MOVL *XAR0, ACC

; Initialize all the DP library macro used here

PWMDRV_1ch_UpDwnCntCompl_INIT 3 ; PWM3A
PWMDRV_1ch_INIT 2

ADC1DRV_1ch_INIT 5
ADC1DRV_1ch_INIT 6
ADC1DRV_1ch_INIT 7
ADC2DRV_1ch_INIT 1
CNTL_2P2Z_INIT 1
CNTL_2P2Z_INIT 2
MATH_EMAVG_INIT 1
MATH_EMAVG_INIT 2
LRETR
;-----------------------------------------------------------------------------------------
; Digital Power library - Interrupt Service Routine

.sect "ramfuncs"

; label to CNTL ISR Run function
.def _DPL_ISR
_DPL_ISR:
ASP ; Align stack
PUSH RB ; Save RB if used
; full context save - push any unprotected registers onto stack
PUSH AR1H:AR0H
PUSH XAR2
PUSH XAR3
PUSH XAR4
PUSH XAR5
PUSH XAR6
PUSH XAR7
PUSH XT
SPM 0 ; set C28 mode
CLRC AMODE
CLRC PAGE0,OVM
SETC INTM ; set interrupt global mask - comment if ISR is nestable
SAVE RNDF32=1 ; FPU registers
; set FPU mode

;-----------------------------------------------------------------------------------------

; call DP library modules

ADC1DRV_1ch 5
ADC1DRV_1ch 6
ADC2DRV_1ch 1
ADC1DRV_1ch 7
CNTL_2P2Z 1
CNTL_2P2Z 2
PWMDRV_1ch_UpDwnCntCompl 3 ; PWM3A
PWMDRV_1ch 2        ;error is occur here!!!!! 

MATH_EMAVG 1
MATH_EMAVG 2

;-----------------------------------------------------------------------------------------
; Interrupt management before exit
;-----------------------------------------------------------------------------------------
; Interrupt management before exit

.if(EPWMn_DPL_ISR=1)

.if(EPWM1)
MOVW DP,#_EPwm1Regs.ETCLR
MOV @_EPwm1Regs.ETCLR,#0x01 ; Clear EPWM1 Int flag
.endif ; EPWM1

.if(EPWM2)
MOVW DP,#_EPwm2Regs.ETCLR
MOV @_EPwm2Regs.ETCLR,#0x01 ; Clear EPWM2 Int flag
.endif ; EPWM2

.if(EPWM3)
MOVW DP,#_EPwm3Regs.ETCLR
MOV @_EPwm3Regs.ETCLR,#0x01 ; Clear EPWM3 Int flag
.endif ; EPWM3

.if(EPWM4)
MOVW DP,#_EPwm4Regs.ETCLR
MOV @_EPwm4Regs.ETCLR,#0x01 ; Clear EPWM4 Int flag
.endif ; EPWM4

.if(EPWM5)
MOVW DP,#_EPwm5Regs.ETCLR
MOV @_EPwm5Regs.ETCLR,#0x01 ; Clear EPWM5 Int flag
.endif ; EPWM5

.if(EPWM6)
MOVW DP,#_EPwm6Regs.ETCLR
MOV @_EPwm6Regs.ETCLR,#0x01 ; Clear EPWM6 Int flag
.endif ; EPWM6

MOVW DP,#_PieCtrlRegs.PIEACK ; Acknowledge PIE interrupt Group 3
MOV @_PieCtrlRegs.PIEACK, #0x4
.endif ; EPWMn_ISR

.if(ADC_DPL_ISR=1)
; Case where ISR is triggered by ADC
MOVW DP,#_AdcRegs.ADCINTFLGCLR
MOV @_AdcRegs.ADCINTFLGCLR,#0x01 ; Clear ADCINT1 Flag

MOVW DP,#_PieCtrlRegs.PIEACK ; Acknowledge PIE interrupt Group 1
MOV @_PieCtrlRegs.PIEACK,#0x1
.endif

;-----------------------------------------------------------------------------------------
; full context restore
CLRC INTM ; clear interrupt global mask
RESTORE ; FPU registers

POP XT
POP XAR7
POP XAR6
POP XAR5
POP XAR4
POP XAR3
POP XAR2
POP AR1H:AR0H
POP RB ; Restore RB
NASP ; Un-align stack
;-----------------------------------------------------------------------------------------
IRET ; return from interrupt

;;;;;;;;;;;;;;;;;;;;;;

Main code :::::::::::::::

#include "Boost-Includes.h"

void DeviceInit(void);

#ifdef FLASH_F28M35x
void InitFlash();
#endif
void MemCopy();

#ifdef FLASH_F28M35x
#pragma CODE_SECTION(Inv_ISR,"ramfuncs");
#endif
__interrupt void Inv_ISR(void);

#pragma INTERRUPT (DPL_ISR, HPI)
#pragma INTERRUPT (Inv_ISR, LPI)

//------------------------------- DPLib ----------------------------------------------
void PWM_1ch_UpDwnCntCompl_CNF(int16 n, int16 period, int16 mode, int16 phase);
void ADC_CNF(int AdcNum, int ChSel[], int TrigSel[], int ACQPS[]);
void PWM_1ch_CNF(int16 n, int16 period, int16 mode, int16 phase);

// ---------------------------- FRAMEWORK --------------------------------------------
// State Machine function prototypes
//------------------------------------------------------------------------------------
// Alpha states
void A0(void); //state A0
void B0(void); //state B0
void C0(void); //state C0

// A branch states
void A1(void); //state A1
void A2(void); //state A2
void A3(void); //state A3
void A4(void); //state A4

// B branch states
void B1(void); //state B1
void B2(void); //state B2
void B3(void); //state B3
void B4(void); //state B4

// C branch states
void C1(void); //state C1
void C2(void); //state C2
void C3(void); //state C3
void C4(void); //state C4

// Variable declarations
void (*Alpha_State_Ptr)(void); // Base States pointer
void (*A_Task_Ptr)(void); // State pointer A branch
void (*B_Task_Ptr)(void); // State pointer B branch
void (*C_Task_Ptr)(void); // State pointer C branch
//----------------------------------------------------------------------------------

//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// VARIABLE DECLARATIONS - GENERAL
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// -------------------------------- FRAMEWORK --------------------------------------

int16 VTimer0[4]; // Virtual Timers slaved off CPU Timer 0
int16 VTimer1[4]; // Virtual Timers slaved off CPU Timer 1
int16 VTimer2[4]; // Virtual Timers slaved off CPU Timer 2

// Used for running BackGround in flash, and ISR in RAM
extern Uint16 *RamfuncsLoadStart, *RamfuncsLoadEnd, *RamfuncsRunStart;
// Used for copying CLA code from load location to RUN location
extern Uint16 Cla1funcsLoadStart, Cla1funcsLoadEnd, Cla1funcsRunStart;

// Used for ADC Configuration
int ChSel1[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
int TrigSel1[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
int ACQPS1[16] = {8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8};

int ChSel2[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
int TrigSel2[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
int ACQPS2[16] = {8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8};

// Used to indirectly access all EPWM modules
volatile struct EPWM_REGS *ePWM[] =
{ &EPwm1Regs, //intentional: (ePWM[0] not used)
&EPwm1Regs,
&EPwm2Regs,
&EPwm3Regs,
&EPwm4Regs,
&EPwm5Regs,
&EPwm6Regs,
&EPwm7Regs,
&EPwm8Regs,
&EPwm9Regs
};

// Used to indirectly access all Comparator modules
volatile struct COMP_REGS *Comp[] =
{ &Comp1Regs, //intentional: (Comp[0] not used)
&Comp1Regs,
&Comp2Regs,
&Comp3Regs,
&Comp4Regs,
&Comp5Regs,
&Comp6Regs
};

volatile struct ADC_REGS *ADC[] =
{ &Adc1Regs, //intentional: (ADC[0] not used)
&Adc1Regs,
&Adc2Regs
};
// ---------------------------- DPLIB Net Pointers ---------------------------------
// Declare net pointers that are used to connect the DP Lib Macros here

// ADCDRV_1ch
extern volatile float *ADC1DRV_1ch_Rlt5; //instance #2
extern volatile float *ADC1DRV_1ch_Rlt6; //instance #3
extern volatile float *ADC1DRV_1ch_Rlt7; //instance #5

extern volatile float *ADC2DRV_1ch_Rlt1; // instance #1

// PWMDRV_1ch
//extern volatile float *PWMDRV_1ch_Duty3; // instance #3, EPWM3
extern volatile float *PWMDRV_1ch_UpDwnCntCompl_Duty3;
extern volatile float PWMDRV_1ch_UpDwnCntCompl_Period3;
extern volatile float *PWMDRV_1ch_Duty2;
extern volatile float PWMDRV_1ch_Period2;

// CONTROL_2P2Z
extern volatile float *CNTL_2P2Z_Ref1; // instance #1
extern volatile float *CNTL_2P2Z_Out1; // instance #1
extern volatile float *CNTL_2P2Z_Fdbk1; // instance #1
extern volatile float *CNTL_2P2Z_Coef1; // instance #1
extern volatile float CNTL_2P2Z_DBUFF1[5];

// CONTROL_2P2Z
extern volatile float *CNTL_2P2Z_Ref2; // instance #1
extern volatile float *CNTL_2P2Z_Out2; // instance #1
extern volatile float *CNTL_2P2Z_Fdbk2; // instance #1
extern volatile float *CNTL_2P2Z_Coef2; // instance #1
extern volatile float CNTL_2P2Z_DBUFF2[5];

//MATH_EMAVG - instance #1
extern volatile float *MATH_EMAVG_In1;
extern volatile float *MATH_EMAVG_Out1;
extern volatile float MATH_EMAVG_Multiplier1;

//MATH_EMAVG - instance #2
extern volatile float *MATH_EMAVG_In2;
extern volatile float *MATH_EMAVG_Out2;
extern volatile float MATH_EMAVG_Multiplier2;


// ---------------------------- DPLIB Variables ---------------------------------
// Declare the net variables being used by the DP Lib Macro here

volatile float Duty3A,Duty3A_fixed;
volatile float VboostRead;
volatile float VpvRef;
volatile float VpvRead, IpvRead;
volatile float VpvRead_EMAVG, IpvRead_EMAVG;
volatile float IboostswRead;
volatile float IboostSwRef;
volatile float IboostSwRef2;
volatile float VpvRef_MPPT;

#pragma DATA_SECTION(CNTL_2P2Z_CoefStruct1, "CNTL_2P2Z_Coef");
struct CNTL_2P2Z_CoefStruct CNTL_2P2Z_CoefStruct1;

#pragma DATA_SECTION(CNTL_2P2Z_CoefStruct2, "CNTL_2P2Z_Coef");
struct CNTL_2P2Z_CoefStruct CNTL_2P2Z_CoefStruct2;

float Pgain_V,Igain_V,Dgain_V,Dmax_V;
float Pgain_I,Igain_I,Dgain_I,Dmax_I;

int16 UpdateCoef;

Uint16 i;
int16 LedBlinkCnt,LedBlinkCnt2;

void main(void)
{
//=================================================================================
// INITIALISATION - General
//=================================================================================

DeviceInit(); // Device Life support & GPIO

// Only used if running from FLASH
// Note that the variable FLASH_F28M35x is defined by the compiler with -d FLASH_F28M35x
#ifdef FLASH_F28M35x
// Copy time critical code and Flash setup code to RAM
// The RamfuncsLoadStart, RamfuncsLoadEnd, and RamfuncsRunStart
// symbols are created by the linker. Refer to the linker files.
MemCopy(&RamfuncsLoadStart, &RamfuncsLoadEnd, &RamfuncsRunStart);

// Call Flash Initialization to setup flash waitstates
// This function must reside in RAM
InitFlash(); // Call the flash wrapper init function
#endif //(FLASH)

// On Concerto the comparator output is not mapped internally to the PWM TZ
// The comparator output needs to be brought out on a AGPIO pin and then routed to a GPIO on the C28x side
// COMP1 which is the Boost Voltage compare out is brought out on AGPIO1 i.e. pin 129 on #144 package
// This selection is done in the AGPIO section in the DevInit File
// The pin 129 is connected on the concerto control card to PF3_GPIO35 which is configured as a trip source below

EALLOW;
GpioTripRegs.GPTRIP10SEL.bit.GPTRIP10SEL =35; //Map Trip input 10 (COMP1OUT) to PF3_GPIO35
EDIS;

//-------------------------------- FRAMEWORK --------------------------------------

// Timing sync for background loops
CpuTimer0Regs.PRD.all = mSec5; // A tasks
CpuTimer1Regs.PRD.all = mSec50; // B tasks
CpuTimer2Regs.PRD.all = mSec1000; // C tasks

// Tasks State-machine init
Alpha_State_Ptr = &A0;
A_Task_Ptr = &A1;
B_Task_Ptr = &B1;
C_Task_Ptr = &C1;

VTimer0[0] = 0;
VTimer1[1] = 0;
VTimer2[2] = 0;

for (i=0; i<16; i++)
{
ChSel1[i] = 0;
TrigSel1[i] = 0;
ACQPS1[i] = 8;

ChSel2[i] = 0;
TrigSel2[i] = 0;
ACQPS2[i] = 8;
}

// ---------------------------------- USER -----------------------------------------
// put common initialization/variable definitions here


LedBlinkCnt = 5;

// ---------------------------------- USER -----------------------------------------
///////

// configure the PWM1 for the inverter driver
// 20Khz = (150Mhz/20Khz)/2 = 3750
// From the datasheet of the mosfet used the Ton and Toff is 264ns
// therefore 150 Mhz => ~40 Ticks
// PWM_1phInv_unipolar_CNF(1,3750,40,40);

// Configure PWM3 for 100Khz switching Frequency
//Period Count= 150Mhz/100Khz = 1500
PWM_1ch_UpDwnCntCompl_CNF(3,1500,1,350);
PWM_1ch_CNF(2,1500,1,0);


// SOC for DCDC Boost MPPT
EPwm3Regs.ETSEL.bit.SOCAEN = 1;
EPwm3Regs.ETSEL.bit.SOCASEL = ET_CTR_PRD ; // Use PRD event as trigger for ADC SOC
EPwm3Regs.ETPS.bit.SOCAPRD = ET_2ND; // Generate pulse on 2nd event

// #define Ileg1_fb Adc1Result.ADCRESULT1
// #define Ileg2_fb Adc1Result.ADCRESULT2
// #define Vac_FB Adc1Result.ADCRESULT3
// #define Ipv_FB Adc1Result.ADCRESULT5
// #define Vpv_FB Adc1Result.ADCRESULT6
// #define Vboost_FB Adc1Result.ADCRESULT7
//
// #define Iboostsw_FB Adc2Result.ADCRESULT1
// #define LIGHT_FB Adc2Result.ADCRESULT2

// ADC Channel Selection

ChSel1[0] = 4; //ADC1 SOC 0 -> Ileg1-fb -> ADC1-A4 on F28M3x rev 1.0 -> ADC-A4 {Piccolo}, dummy
ChSel1[1] = 4; //ADC1 SOC 0 -> Ileg1-fb -> ADC1-A4 on F28M3x rev 1.0 -> ADC-A4 {Piccolo}
ChSel1[2] = 6; //ADC1 SOC 1 -> Ileg2-fb -> ADC1-A6 on F28M3x rev 1.0 -> ADC-A6 {Piccolo}
ChSel1[3] = 7; //ADC1 SOC 4 -> Vac-fb -> ADC1-A7 on F28M3x rev 1.0 -> ADC-A5 {Piccolo}
ChSel1[4] = 0; //ADC1 SOC 2 -> Ipv-fb -> ADC1-A0 on F28M3x rev 1.0 -> ADC-A0 {Piccolo}, dummy
ChSel1[5] = 0; //ADC1 SOC 2 -> Ipv-fb -> ADC1-A0 on F28M3x rev 1.0 -> ADC-A0 {Piccolo}
ChSel1[6] = 8; //ADC1 SOC 3 -> Vpv-fb -> ADC1-B0 on F28M3x rev 1.0 -> ADC-A1 {Piccolo}
ChSel1[7] = 2; //ADC1 SOC 5 -> Vboost-fb -> ADC1-A2 on F28M3x rev 1.0 -> ADC-A2 {Piccolo}

// ADC Trigger Selection

TrigSel1[0] = 6; // ADC1 SOC 0 -> Ileg1-fb, dummy
TrigSel1[1] = 6; // ADC1 SOC 0 -> Ileg1-fb
TrigSel1[2] = 6; // ADC1 SOC 1 -> Ileg2-fb
TrigSel1[3] = 6; // ADC1 SOC 4 -> Vac-fb
TrigSel1[4] = 5; // ADC1 SOC 2 -> Ipv-fb , dummy
TrigSel1[5] = 5; // ADC1 SOC 2 -> Ipv-fb
TrigSel1[6] = 5; // ADC1 SOC 3 -> Vpv-fb
TrigSel1[7] = 5; // ADC1 SOC 5 -> Vboost-fb

// Let Trigger 1 be used for the Boost Control and the Trigger 2 be used for the inverter control
// Configure the CIB triggers (Note this needs to be done before the ADC SOC trigger selection)

EALLOW;
AnalogSysctrlRegs.TRIG1SEL.all = ADCTRIG_EPWM3_SOCA; // EPWM3SOCA to TRIGGER 1 of the analog subsystem
AnalogSysctrlRegs.TRIG2SEL.all = ADCTRIG_EPWM1_SOCA; // EPWM1SOCA to Trigger 2 of the analog subsystem
EDIS;

ADC_CNF(1, ChSel1, TrigSel1, ACQPS1);

// ADC Channel Selection

ChSel2[0] = 6; //ADC2 SOC 0 -> Iboostsw-fb-> ADC2-A6 on F28M3x rev 1.0 -> ADC-B6 {Piccolo}
ChSel2[1] = 6; //ADC2 SOC 0 -> Iboostsw-fb-> ADC2-A6 on F28M3x rev 1.0 -> ADC-B6 {Piccolo}
ChSel2[2] = 0; //ADC2 SOC 1 -> Vlight-fb -> ADC2-A0 on F28M3x rev 1.0 -> ADC-B0 {Piccolo}

// ADC Trigger Selection
TrigSel2[0] = 5; // ADC2 SOC 0 -> Iboostsw-fb, dummy
TrigSel2[1] = 5; // ADC2 SOC 0 -> Iboostsw-fb
TrigSel2[2] = 6; // ADC2 SOC 2 -> Vlight-fb

ADC_CNF(2, ChSel2, TrigSel2, ACQPS2);

// Digital Power CLA(DP) library initialisation
DPL_Init();

// Lib Module connection to "nets"
//----------------------------------------
// Connect the PWM Driver input to an input variable, Open Loop System
//
PWMDRV_1ch_UpDwnCntCompl_Duty3 = &Duty3A_fixed; //&Duty3A; //&Duty3A_fixed;
PWMDRV_1ch_Duty2 = &Duty3A_fixed; //&Duty3A; //&Duty3A_fixed;


// ADC2DRV_1ch_Rlt1 = &IboostswRead;
//
// ADC1DRV_1ch_Rlt5 = &IpvRead;
// ADC1DRV_1ch_Rlt6 = &VpvRead;
// ADC1DRV_1ch_Rlt7 = &VboostRead;
//
// // MATH_EMAVG1 block connections
// MATH_EMAVG_In1=&IpvRead;
// MATH_EMAVG_Out1=&IpvRead_EMAVG;
// MATH_EMAVG_Multiplier1=0.001; // a 1000 point moving average filter
//
// // MATH_EMAVG2 block connections
// MATH_EMAVG_In2=&VpvRead;
// MATH_EMAVG_Out2=&VpvRead_EMAVG;
// MATH_EMAVG_Multiplier2=0.001; // a 1000 point moving average filter

//======================================================================================
//connect the 2P2Z connections, for the inner current Loop

// CNTL_2P2Z_Ref2 = &IboostSwRef;
// CNTL_2P2Z_Out2 = &Duty3A;
// CNTL_2P2Z_Fdbk2= &IboostswRead;
// CNTL_2P2Z_Coef2 = &CNTL_2P2Z_CoefStruct2.b2;
//
// //connect the 2P2Z connections, for the outer Voltage Loop
// CNTL_2P2Z_Ref1 = &VpvRead;
// CNTL_2P2Z_Fdbk1 = &VpvRef;
// CNTL_2P2Z_Out1 = &IboostSwRef;
// CNTL_2P2Z_Coef1 = &CNTL_2P2Z_CoefStruct1.b2;

// Coefficients for Outer Voltage Loop
// PID coefficients & Clamping - Current loop
// Dmax_V = 0.9;
// Pgain_V = 0.015;
// Igain_V = 0.00005;
// Dgain_V = 0.0;

// Coefficient init
// CNTL_2P2Z_CoefStruct1.b2 =Dgain_V; // B2
// CNTL_2P2Z_CoefStruct1.b1 =(Igain_V-Pgain_V-Dgain_V-Dgain_V); // B1
// CNTL_2P2Z_CoefStruct1.b0 =(Pgain_V + Igain_V + Dgain_V); // B0
// CNTL_2P2Z_CoefStruct1.a2 =0.0; // A2 = 0
// CNTL_2P2Z_CoefStruct1.a1 =1.0; // A1 = 1
// CNTL_2P2Z_CoefStruct1.max =Dmax_V; //Clamp Hi
// CNTL_2P2Z_CoefStruct1.min =0.0; //Clamp Min

// Coefficients for Inner Current Loop
// PID coefficients & Clamping - Current loop

// Dmax_I = 0.95;
// Pgain_I = 0.015;
// Igain_I = 0.00005;
// Dgain_I = 0.0;

// Coefficient init
// CNTL_2P2Z_CoefStruct2.b2 =Dgain_I; // B2
// CNTL_2P2Z_CoefStruct2.b1 =(Igain_I-Pgain_I-Dgain_I-Dgain_I); // B1
// CNTL_2P2Z_CoefStruct2.b0 =(Pgain_I + Igain_I + Dgain_I); // B0
// CNTL_2P2Z_CoefStruct2.a2 =0.0; // A2 = 0
// CNTL_2P2Z_CoefStruct2.a1 =1.0; // A1 = 1
// CNTL_2P2Z_CoefStruct2.max =Dmax_I; //Clamp Hi
// CNTL_2P2Z_CoefStruct2.min =0.0; //Clamp Min

// Initialize the net variables

// Duty3A =0.0;
// VboostRead=0.0;
// IboostswRead=0.0;
// VpvRef=0.9; // to increase current, we need to reduce VpvRef, thus initailize it with a high value.
// IboostSwRef=0.0;
// Duty3A_fixed=0.0;
// VpvRead_EMAVG=0.0;
// IpvRead_EMAVG=0.0;

// MPPT testing related code
// mppt incc

// mppt_incc1.IpvH = 0.0001;
// mppt_incc1.IpvL = -0.0001;
// mppt_incc1.VpvH = 0.0001;
// mppt_incc1.VpvL = -0.0001;
// mppt_incc1.MaxVolt = 0.9;
// mppt_incc1.MinVolt = 0.0;
// mppt_incc1.Stepsize = 0.005;
// mppt_incc1.mppt_first=1;
// mppt_incc1.mppt_enable=0;

//mppt pno

// mppt_pno1.DeltaPmin = 0.00001;
// mppt_pno1.MaxVolt = 0.9;
// mppt_pno1.MinVolt = 0.0;
// mppt_pno1.Stepsize = 0.005;
//
// MPPT_method=0;

//Inverter

// Signal Generator module initialisation

// sgen.offset=0;
// sgen.gain=0x7fff; // gain=1 in Q15
// sgen.freq=0x14F8CF92; // freq = (Required Freq/Max Freq)*2^31
// // = (50/305.17)*2^31 = 0x14f8cf92
// sgen.step_max=0x3E7FB26; // Max Freq= (step_max * sampling freq)/2^32
// // =(0x3E7FB26*20k)/2^32 = 305.17
// sgen.phase=0x80000000; // Phase= (required Phase)/180 in Q31 format
// // = (+90/180) in Q31 = 8000h
//
// //sine analyzer initialization
// sine_mainsV.Vin=0;
// sine_mainsV.SampleFreq=20000.0;
// sine_mainsV.Threshold=0.0;

// Initialize DATALOG module
/* dlog.iptr1 = &DlogCh1;
dlog.iptr2 = &DlogCh2;
dlog.iptr3 = &DlogCh3;
dlog.iptr4 = &DlogCh4;
dlog.trig_value = _IQ15(0.08);
dlog.size = 0x64;
dlog.prescalar = 10;
dlog.init(&dlog);
*/

// pidGRANDO_Iinv.param.Kp=0.8;
// pidGRANDO_Iinv.param.Ki=(0.15);
// pidGRANDO_Iinv.param.Kd=(0.0);
// pidGRANDO_Iinv.param.Kr=(1.0);
// pidGRANDO_Iinv.param.Umax=(1.0);
// pidGRANDO_Iinv.param.Umin=(-1.0);
//
// // Initialize PWMDAC module
// pwmdac1.PeriodMax = 500; // 3000->10kHz, 1500->20kHz, 1000-> 30kHz, 500->60kHz
// pwmdac1.PwmDacInPointer0 = &PwmDacCh1;
// pwmdac1.PwmDacInPointer1 = &PwmDacCh2;
// pwmdac1.PwmDacInPointer2 = &PwmDacCh3;
// pwmdac1.PwmDacInPointer3 = &PwmDacCh4;
//
//
//
// pidGRANDO_Vinv.param.Kp=(3.0);
// pidGRANDO_Vinv.param.Ki=(0.005);
// pidGRANDO_Vinv.param.Kd=(0.0);
// pidGRANDO_Vinv.param.Kr=(1.0);
// pidGRANDO_Vinv.param.Umax=(0.95);
// pidGRANDO_Vinv.param.Umin=(0.000);
//
// PWMDAC_INIT_MACRO(pwmdac1)
//
// SPLL_1ph_init(GRID_FREQ,(0.00005),&spll1);
//
// PanelBoostConnect=0;
// MPPT_ENABLE = 0;
// Run_MPPT=0;
// MPPT_slew=0;
// VpvRef_MPPT=(0.0);
//
// CloseVloopInv = 0;
// CloseIloopInv = 0;
// ClearInvTrip=0;
// InvModIndex = 0;
// ScaleFactor = (1.0);
// inv_Iset = (0.0);
// InvSine=0;
// VrmsReal=0;
//
// UpdateCoef=0;
// timer1=0;
// Offset_Volt=(0.5); // the input sinusoid is offset with 1.65 V
//
// PVInverterState=0;
// Gui_MPPTEnable=0;
// Gui_InvStart=0;
// Gui_InvStop=0;
//
// // keep the PLL in reset by default
// ResetPLL=1;
//
// Gui_LightCommand=0.0;
//
//====================================================================================
// INTERRUPTS & ISR INITIALIZATION (best to run this section after other initialization)
//====================================================================================

//Also Set the appropriate # define's in the HVLLC-Settings.h
//to enable interrupt management in the ISR
EALLOW;
// Set up C28x Interrupt

// PWM based ISR trigger, Boost DC DC Interrupt
PieVectTable.EPWM3_INT = &DPL_ISR; // Map DPL Interrupt from EPWM3

PieCtrlRegs.PIEIER3.bit.INTx3 = 1; // PIE level enable, Grp3 / Int3 -> EPWM3

EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_PRD; // INT on PRD event
EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm3Regs.ETPS.bit.INTPRD = ET_2ND; // Generate INT on every second event

//PWM Based ISR Trigger, Inverter
PieVectTable.EPWM1_INT = &Inv_ISR; // Map DPL Interrupt from EPWM1

PieCtrlRegs.PIEIER3.bit.INTx1 = 1; // PIE level enable, Grp3 / Int1 -> EPWM1

EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // INT on zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on every event

IER |= M_INT3; // Enable CPU INT3 connected to EPWM1-6 INTs:

EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM

EDIS;


// Protection for over voltage on the Boost
// Vboost-fb is mapped to ADC2 -> A2 which is also connected to Comparator 4

// EALLOW;
// Comp1Regs.COMPCTL.bit.COMPDACEN = 1; // Power up Comparator 1 locally
// Comp1Regs.COMPCTL.bit.COMPSOURCE = 0; // Connect the inverting input to the internal DAC
// Comp1Regs.DACVAL.bit.DACVAL = 950; // Set DAC output to midpoint
//
// // cannot disable hysteresis for now on COMP1 , need to identify the bit field from product apps
// Adc1Regs.COMPHYSTCTL.bit.COMP1_HYST_DISABLE=1;
//
// EDIS;
///////////////////////////////////////////////////////////////////////////////////////////////////////////

// EALLOW;
//
// // Cycle by cycle trip for overvoltage protection
// // The code below is a mess! nobodfy knows what's on Sonata!
// // Not sure why it needs ot be DC_COMNP2OUT for COMP5OUT
// EPwm3Regs.DCTRIPSEL.bit.DCAHCOMPSEL=DC_COMP2OUT;
// EPwm3Regs.TZDCSEL.bit.DCAEVT2=TZ_DCAH_HI;
//
// EPwm3Regs.DCACTL.bit.EVT2SRCSEL = DC_EVT1;
// EPwm3Regs.DCACTL.bit.EVT2FRCSYNCSEL=DC_EVT_ASYNC;
//
// EPwm3Regs.TZSEL.bit.DCAEVT2=0x1;
//
// // Define an event (DCAEVT1) based on TZ1 and TZ2
// EPwm3Regs.DCAHTRIPSEL.bit.TRIPINPUT10 = 1; // Map Trip input 10(COMP2OUT) to DCAH
//
// // What do we want the DCAEVT1 and DCBEVT1 events to do?
// // DCAEVTx events can force EPWMxA
// // DCBEVTx events can force EPWMxB
// EPwm3Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
// EPwm3Regs.TZCTL.bit.TZB = TZ_FORCE_LO;
//
// EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
// EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO;
// EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
// EPwm2Regs.TZCTL.bit.TZB = TZ_FORCE_LO;
//
// // CBC6 is still CPU EMU trip, no doc tells if this is true so just guessing
// EPwm3Regs.TZSEL.bit.CBC6=0x1;
// EPwm1Regs.TZSEL.bit.CBC6=0x1;
// EPwm2Regs.TZSEL.bit.CBC6=0x1;
//
// EPwm3Regs.TZEINT.bit.CBC=1;
//
// //clear any spurious trips
// EPwm3Regs.TZCLR.bit.OST=1;
// EPwm3Regs.TZCLR.bit.DCAEVT1=1;
//
// // software force the trip of inverter to disable the inverter completely
// EPwm1Regs.TZFRC.bit.OST=0x1;
// EPwm2Regs.TZFRC.bit.OST=0x1;
// EDIS;

// connect the panel output to the Boost input
// Run_MPPT=0;
//
//
// VpvRef_MPPT=0.0;
//
// MPPT_slew=0;

//=================================================================================
// BACKGROUND (BG) LOOP
//=================================================================================

//--------------------------------- FRAMEWORK -------------------------------------
for(;;) //infinite loop
{
// State machine entry & exit point
//===========================================================
(*Alpha_State_Ptr)(); // jump to an Alpha state (A0,B0,...)
//===========================================================
}
}