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CPU and DMA XINTF concurrent access (F28335)

Hi,

In the document SPRUFB8 (DMA), it is explained the CPU arbitration when DMA and CPU are accessing both the XINTF interface.

In my application, I have a DMA that is moving data from XINTF0 (FPGA) to XINTF6 (external SRAM).

Because the FPGA is at low speed, there are several wait states set on XINTF0.

Every 1ms, 500us are required by the DMA to move the data (big buffer of several KW). The DMA transfer is requiring 15 cycles.

In parallel, the CPU is processing data that are store in the external SRAM (so has to use also the shared XINTF).

Could you explain in details the arbitration in this case ?

Is it possible to evaluate how long the CPU will be stall ? same thing for the DMA ?

Thanks for your help

Regards,

Mathieu

  • Mathiew,

    You may want to consider copying the external SRAM data into the internal RAM, and then running your computations. In this way the CPU won't be stalled and your computation time will be deterministic.

    Regards,
    Bill