In my design, I planned the PWM's and the ADC's in core 1 and SPI and QEP in CPU02. All of the functions already were tested on cpu1 and run brilliantly, also SpiA in Hi-speed mode at 20 MHz, using pins 58...61
I am new on TI, CCS, but I am impressed by the easines of documentation, until now:
To learn how to run SPI on cpu2, I tried to change the Example spi_loopback_dma, without success.
I initiated all of the GPIO and the SPI-registers in cpu1 as GPIO's can not be initiated in Cpu2.
GpioCtrlRegs.GPBLOCK.bit.GPIO58 = 0;// etc. for the pins 59, 60 and 61
GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // Asynch etc.
GpioCtrlRegs.GPBGMUX2.bit.GPIO58 = 3; //spi hi-speed etc(take care: the documentation talks 0x11 instead of 11b)
GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 3; // id. etc
To set SPI in HiSpeed:
SpiaRegs.SPICCR.bit.HS_MODE = 1; // "Reserved bit5" Hispeed mode
Then I changed ownership of SPI and GPIO-pins to Cpu2
GpioCtrlRegs.GPBCSEL4.bit.GPIO58 = 2;// etc, for 59...61 cpu2
DevCfgRegs.DEVCFGLOCK1.bit.CPUSEL6 = 0; // unlock
DevCfgRegs.CPUSEL6.bit.SPI_A = 1; // spi to cpu2
DevCfgRegs.DEVCFGLOCK1.bit.CPUSEL6 = 1; // lock
----until here everything is done in cpu1.
In CPU2 the DMA code is initiated without change from the example code as I understand that each core has its own DMA and registers.
Point is that this is a trial and error approach as there are no example codes for running peripherals on cpu2.
Is there some documentation that I missed? or am I the first to do this? In order to find the many things that I do wrong, I need to know which of the code is securely correct according to TI . Most importantly, what are the rules for initiating Spi in CPu2
Pls help.
Henk Schutte
Amsterdam
