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Valid XTIMING register configuration for X2TIMING=1

Uwe Grossmann
Prodigy 40 points

I'm using 28346 external interface XINTF with following configuration:

USEREADY=0, X2TIMING=0, LR=3, AR=7, TR=0, LW=3, AW=4, TW=3

In this configuration LR, AR, LW and TW are at the maximum and can't be increased anymore.

To increase the wait states I need to set X2TIMING = 1.

The  restrictions for X2TIMING=0, USEREADY=0 are:

LR>=2, AR>=6, TR>=0, LW>=3, AW>=1, TW>=3

The Data Sheet says: "If X2TIMING is enabled, specified Lead, Acitve, and Trail restrictions can be divided by 2 for values with even numbers."

An appropriate configuration (from my external IC point of view) would be:

X2TIMING=1, LR=2, AR=4, TR=0, LW=2, AW=2, TW=2

Is this a valid configuration?

Thanks for an clarification.

Uwe Grossmann

  • 0
    TI__Guru** 109165 points

    Hi,

    Not sure if I understand your concern here but the configuration you provided (X2TIMING=1, LR=2, AR=4, TR=0, LW=2, AW=2, TW=2) look perfectly fine to me as long as it meets the external memory timing.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Prodigy 40 points

    Hi Vivek,

    my concern is the correct interpretation of the footnote in the manual: "If X2TIMING is enabled, specified Lead, Acitve, and Trail restrictions can be divided by 2 for values with even numbers."

    For example, the restriction for Lead Write stated in the manual is LW>= 3. 3 is not an even number. Does the footnote mean that LW has to be greater or equal to 3 if X2TIMING is enabled? In this case my configuration would be invalid.

    Thanks for your answer.

    Regards,

    Uwe Grossmann

  • 0 in reply to Uwe Grossmann
    TI__Guru** 109165 points

    Hi,

    Sorry for late reply. The footnote in the manual is there to make sure when user enable the X2TIMING, they can change the Lead/Active/Trail timaing accordingly becasue memory access timing remains same.

    With X2TIMING = 1, LW >= 2, so your configuration is valid.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Prodigy 40 points

    Hi,

    to put it with my words:

    1. If X2TIMCLK is anabled, Lead, Active and Trail restrictions are the speciefied restrictions divided by 2 and rounded to the next greater integer.

    From your statement that "memory access timing remains the same", I conclude that:

    2. If XTIMCLK is one half  of SYSCLKOUT (XINTCNF2.bit.XTIMCLK = 1), Lead, Active and Trail restrictions are the speciefied restrictions divided by 2 and rounding to the next greater integer.

    Could you please confirm or dismiss the two statements. Thanks.

    Uwe Grossmann

  • 0 in reply to Uwe Grossmann
    TI__Guru** 109165 points

    Hi,

    Both of your statements are correct.

    Regards,

    Vivek Singh