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ECAP 85 Mhz frequency measurement

I have a question regarding timing of Piccolo F2807x. I want to use it to measure the frequency of a an 85 Mhz sine wave signal. I am planning to use ecap module. Mz idea is to capture two rising edge of this signal and then store the value of the TSCTR to calculate from this the frequency just like in example 3 in  

From my understanding there is no need to divide the signal as long we have a system clock that is running at least with the frequency of the signal or more but there is also the option to use a prescaler and work with lower frequency system clock is that right? or is that ecap can not catch such a high frequency signal?

Thanks.

  • Christos,

    The eCAP on F2807x is going to have a minimum captured pulse width of 2*tc(SYSCLK), where SYSCLK is the frequency of the CPU (e.g., 120 MHz on F2807x devices). I pulled this information from the similar device F2837xD datasheet, SPRS880C, p.130, which is a bit ahead in development. The same information will eventually be put in the F2807x datasheet. So, you cannot measure the frequency of an 85 MHz signal using a 120 MHz F2807x. You'd need at least 2*85 = 170 MHz device to catch 85 MHz edges.

    Let's put that issue aside for a minute, and let's just suppose you were using the 200 MHz F2837xD or F2837xS devices and therefore could theoretically measure the 85 MHz edges. Your frequency resolution would be terrible! I mean, you'd have 5 ns resolution on the edges. 85 MHz is 11.76 ns edges, but you cannot read that. You'd get either 10 ns or 15 ns. Also, you'd need a comparator to square up the sinewave.

    Thinking out loud here, a better approach may be to use the eQEP module in up-count mode along with the eQEP unit time base sub-module. You'll need a divide-by-two (simple D flip-flop) on your sinewave prior to feeding into the eQEP. You set the unit time base to latch the counter value at an appropriate interval for the resolution you want for the frequency. Then read the latched counter value and divide by the interval. See the picture? See the F2837xD TRM, SPRUHM8C chapter 16 for info on the eQEP.

    Regards,
    - David
  • Correct me if I am wrong but in our case we are not capturing the pulse width but two positive edges of the incoming signal which is in fact two pulses so double the time, which make us capable (with low resolution indeed) to work with 85 MHz. Additionally we could use prescaler to increase accuracy. 

  • I believe the spec is saying that the time between two consecutive capture edges must be at least 2*tc(SYSCLK).  Whether these edges are both rising, both falling, or one rising and the other falling doesn't matter.  Consider the below figure, representative of your setup.  Your input waveform is 11.76 ns (85 MHz).  The system clock is 8.33 ns (120 MHz).  Suppose the rising edges of SYSCLK align how I marked tc(SYSCLK) below, and suppose the eCAP latches the value of the input waveform on the rising edges (similar for falling edges, I don't know which edge the latching occurs on).  The eCAP unit will see the input pin high on both rising edges, and therefore will not trigger the second capture since it thinks the input waveform has not changed.

    This is why you need the input waveform to be no faster than 2*tc(SYSCLK).  The eCAP unit needs to see the state changes.

    Regards,

    David

  • What if we use the prescaler? Then it works but with low resolution as you mentioned. For example with 62 prescaler if we run at 120 MHz is (120/85/62) 85 Samples per cycle which give us 1% error.
  • I think you still need to meet the tc(SYSCLK) requirement on the incoming waveform. The prescaler will then divide things down from there.

    - David
  • Hallo David,

    Thanks once again for the answers. I read yesterday eQEP module, it's rather complicate for me in the beginning. If I go with this approach then the system clock has to be 200 MHz or less? (I suppose 200 Mhz otherwise I can still use Piccolo). And I suppose this Flip-Flop that you mentioned has to be an external IC right? In the beginning of this project I was using an FPGA to increment a counter for 1 ms and then count the number of pulses to determinate the frequency. This approach is similar with what you suggested. Now I want to switch to a microcontroller based solution, the main issues is temperature (Automotive grade -40-125 C) small package (not BGA less than 15x15 mm) and I want to keep external components as less as possible. The solution you mentioned sounds very promising is there are any other TI microcontroller that could made the job? Sorry for the high umber of questions only the firs two are important you can ignore the last one.

    Regards

    Christos

  • Christos,

    Christos Karatzoglou said:
    If I go with this approach then the system clock has to be 200 MHz or less? (I suppose 200 Mhz otherwise I can still use Piccolo).

    Other C2000 devices have the same requirement that the frequency of the input signal be no greater than half the system clock.  You have a 85 MHz input signal, so you would need a 170 MHz or greater system clock.  If you use a divide-by-two on the input signal, then you'd have a 42.5 MHz input waveform and need an 85 MHz minimum system clock.

    Christos Karatzoglou said:
    And I suppose this Flip-Flop that you mentioned has to be an external IC right?

    Yes, it would need to be external.

    - David