All:
I am considering using an input clock of 26 MHz on the F28335 part. Overall system clock would be 5x26 MHz = 130 MHz.
1. The biggest reason is it allows me to get to 3.25 MBaud on SCI port.
Using LSPCLK of 52 MHz, and BRR of 1, I can get to 3.25 MBaud.
2. I can still get to 100 KHz on I2C by using setting I2CPSC to value of 12, resulting in divide-by 13.
3. SPI of 1 Mbaud can be obtained by LSPCLK / 52, so the value to put in the register is 51.
4. Surprisingly, it looks like there is no detriment to the flash. At 130 MHz, it looks like I can use Page Wait-State of 4, Random Wait-State of 4, and OTP Wait-state of 7 (Similar to 120 MHz shown in datasheet). This results in a Flash w/pipelining value of 104 MIPs.
So, before I toot my horn too much, does anyone see any flaws in the above?
Also, could I use LSPCLK of 26 MHz? [It seems like either value might work.]
Oh, and McBSP is not being used, nor is CAN, so those would not need to be computed.
