Dear reader(s),
I'm having PWM1 on 100MHz clock with output PWM1A and PWM1B.
PWM1A: Set on CNTR==ZERO event, Cleared on CNTR==PWMA event.
PWM1B: Set on CNTR==ZERO event, Cleared on CNTR==PWMB event.
Both are routed through deadband block:
PWM1A : RISING EDGE delayed,
PWM1B: FALLING EDGE delayed, and inverted (complementairy).
Both are running as High resolution :
n=1;
EPWM[n]->HRCNFG.bit.HRLOAD = HR_CTR_ZERO;
EPWM[n]->HRCNFG.bit.CTLMODE = HR_CMP;
EPWM[n]->HRCNFG.bit.EDGMODE = HR_FEP;
EPWM[n]->HRCNFG.bit.HRLOADB = HR_CTR_ZERO;
EPWM[n]->HRCNFG.bit.CTLMODEB = HR_CMP;
EPWM[n]->HRCNFG.bit.EDGMODEB = HR_FEP;
EPWM[n]->HRCNFG.bit.AUTOCONV = AUTOHR_ENABLE;
EPWM[n]->HRCNFG.bit.SELOUTB = HR_NORM_B;
EPWM[n]->HRPWR.all = 0x8000; //enable HRES CALIBRATION logic.
EPWM[n]->HRMSTEP.all = 66; //default value
EPWM[n]->DBCTL.bit.HALFCYCLE = 1;
Without DeadBand the PWMs are high resolution, but with DB enabled the edges are not high resolution anymore. They are now changing with 5ns steps instead of the expected ~180ps. It seems that DeadBand degrades the high resolution PWM?
Could someone confirm this, or am I missing things?
Best regards