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ADC clock and cpu clock synchronization

stephane stephane
Prodigy 80 points

Hello , 

I am working on controlling the jitter between the cpu clock and the ADC clock , during acquisition sequences.

For instance, i am performing a full sequence acquisition using the sequential mode based on 8 input channels, using SEQ1 sequencer.

Knowing the following steps :

 1- configure the auto conversion mode to OFF

 2- reset the sequencer ,

3-  trigger the SOC 

4- Wait that the SEQ_CNTR reaches 0 (through a loop and ADC status  word)

5- TOGGLE  GPIO5

I expect to have the same number of CPU clocks between steps 4 and 5 each time this full sequence is performed.

I expect no jitter between strep4 and 5 But i still have a jitter of 1 CPU cycle

Did any one face this issue to provide synchronization with the ADC clock ?

Thank you

  • 0
    TI__Guru 60865 points
    Hi Stephane,
    Even if your spin-wait loop is a single C instruction, it will compile to multiple assembly instructions. Because of this, the time from recognizing the ADC status word to toggling the GPIO will jitter. Have you tried using an ISR to see if that gives you more consistent results?