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SPI Problem of Timing

Sandip Rakhasiya
Intellectual 340 points

Hello Sir, 

I am Sandip Rakhasiya. Currently I am using F28M35H52C1 controller.

In which I have used SPI at DSP C28 side. I have used 15 MBPS Bitrate for SPI. Here I have to total transmit/receive 64 data in only 100 microsecond but it nearer to 125 micro second. But Here We have only 16 Fifo so i can not transmit more than 16 words at one time. So I have to transmit 16 words x 4 times.

Now When i am transmitting, there is some gap between regular transmit. I have few picture of CS line. In this CS line, 17-18 microsecond required for transmit and after that 25-28 microsecond, it goes to high and after that new 16 words transmited.

In this way I am not understanding, why CS stayed at high for  25-28 microsecond. Is there any solution to remove this gap ?

  • 0
    Intellectual 340 points
    Hello Sir,

    In Above Image CS low for Data transmit and after that It take some time. I have to manage this time. How can i remove this time?????
  • 0 in reply to Sandip Rakhasiya
    Guru 30330 points
    Sandip,

    Since there is no DMA for SPI on the F28M35x series, you must rely on software to keep the bus saturated. Also, the SPI will keep the SPISTE low as long as there is data available to transmit. How are you detecting that the FIFO is empty and ready to transmit? It looks like you are waiting for the SPISTS to reach 0 and then refilling the buffer to transmit with the next set of data. This will take time to execute and since you let the buffer empty, there will be some time that the SPI is inactive. You can look into breaking up the data into different sized chunks and watching for a different FIFO level to always have the buffer with at least one (or more) word pending transmission.

    -Mark
  • 0 in reply to Mark Labbato
    Guru 30330 points
    Sandip,

    Do you have any more questions? If not and if I have answered your question, please verify the answer to mark the thread closed.

    Thanks,
    Mark