Can anyone confirm? Previous posts seem to indicate that only the M3 core and uDMA have access to SDRAM via EPI, but the technical reference manual has a whole chapter dedicated to C28 access.
From 19.9:
"The EPI peripheral is a shared resource between master subsystem (M3 and μDMA) and control subsystem (C28x and DMA). All masters can access external devices via EPI simultaneously."
I can't find any information on where SDRAM memory would be mapped for access from the C28 side, however. Is it possible that the C28 core only has access to the EPI itself (address lines, CS lines, etc), and not to the memory when it is in SDRAM mode?