Hello,
I think there is a possible error in the I2CMCS register description (SPRUH22G, section 24.6.2, page 1681) for the Master Transmit state:
At the case R/S:1, ACK:0, STOP:1, START:1, RUN:1 the description is: "Repeated START condition followed by a TRANSMIT and STOP condition (master goes to Idle state).". The R/S bit is 1, so it should be a Repeated START, RECEIVE, STOP instead.
BR,
Janos
