Hello.
Project in progress by TMS320F28069. I wat a CAN Interface( a receiving method interrupt). so applying the Programming Examples for the TMS320F281x eCAN (MULTINT2.c) using ControlSUTE examples project(cantobacktobac).
Not Interrupt service routine is called.
Code are as follows:
void main(void)
{
struct ECAN_REGS ECanaShadow;
InitSysCtrl();
InitECanGpio();
DINT;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
// This function is found in F2806x_PieVect.c.
InitPieVectTable();
InitECana(); // Initialize eCAN-A module
ECanaMboxes.MBOX0.MSGID.all = 0x9555AAA0;
ECanaMboxes.MBOX1.MSGID.all = 0x9555AAA1;
ECanaMboxes.MBOX2.MSGID.all = 0x9555AAA2;
ECanaMboxes.MBOX3.MSGID.all = 0x9555AAA3;
ECanaMboxes.MBOX4.MSGID.all = 0x9555AAA4;
ECanaMboxes.MBOX5.MSGID.all = 0x9555AAA5;
ECanaMboxes.MBOX6.MSGID.all = 0x9555AAA6;
ECanaMboxes.MBOX7.MSGID.all = 0x9555AAA7;
ECanaMboxes.MBOX8.MSGID.all = 0x9555AAA8;
ECanaMboxes.MBOX9.MSGID.all = 0x9555AAA9;
ECanaMboxes.MBOX10.MSGID.all = 0x9555AA10;
ECanaMboxes.MBOX11.MSGID.all = 0x9555AA11;
ECanaMboxes.MBOX12.MSGID.all = 0x9555AA12;
ECanaMboxes.MBOX13.MSGID.all = 0x9555AA13;
ECanaMboxes.MBOX14.MSGID.all = 0x9555AA14;
ECanaMboxes.MBOX15.MSGID.all = 0x9555AA15;
ECanaMboxes.MBOX16.MSGID.all = 0x9555AA16;
ECanaMboxes.MBOX17.MSGID.all = 0x9555AA17;
ECanaMboxes.MBOX18.MSGID.all = 0x9555AA18;
ECanaMboxes.MBOX19.MSGID.all = 0x9555AA19;
ECanaMboxes.MBOX20.MSGID.all = 0x9555AA20;
ECanaMboxes.MBOX21.MSGID.all = 0x9555AA21;
ECanaMboxes.MBOX22.MSGID.all = 0x9555AA22;
ECanaMboxes.MBOX23.MSGID.all = 0x9555AA23;
ECanaMboxes.MBOX24.MSGID.all = 0x9555AA24;
ECanaMboxes.MBOX25.MSGID.all = 0x9555AA25;
ECanaMboxes.MBOX26.MSGID.all = 0x9555AA26;
ECanaMboxes.MBOX27.MSGID.all = 0x9555AA27;
ECanaMboxes.MBOX28.MSGID.all = 0x9555AA28;
ECanaMboxes.MBOX29.MSGID.all = 0x9555AA29;
ECanaMboxes.MBOX30.MSGID.all = 0x9555AA30;
ECanaMboxes.MBOX31.MSGID.all = 0x9555AA31;
/* Configure Mailboxes 0-31 as Tx */
ECanaRegs.CANMD.all = 0x00000000;
// Enable all Mailboxes */
// Since this write is to the entire register (instead of a bit
// field) a shadow register is not required.
ECanaRegs.CANME.all = 0xFFFFFFFF;
// Specify that 8 bits will be sent/received
ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX2.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX3.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX4.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX5.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX6.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX7.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX8.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX9.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX10.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX11.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX12.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX13.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX14.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX15.MSGCTRL.bit.DLC = 8;
// Write to the mailbox RAM field of MBOX0 - 15
ECanaMboxes.MBOX0.MDL.all = 0x9555AAA0;
ECanaMboxes.MBOX0.MDH.all = 0x89ABCDEF;
ECanaMboxes.MBOX1.MDL.all = 0x9555AAA1;
ECanaMboxes.MBOX1.MDH.all = 0x89ABCDEF;
ECanaMboxes.MBOX2.MDL.all = 0x9555AAA2;
ECanaMboxes.MBOX2.MDH.all = 0x89ABCDEF;
ECanaMboxes.MBOX3.MDL.all = 0x9555AAA3;
ECanaMboxes.MBOX3.MDH.all = 0x89ABCDEF;
ECanaMboxes.MBOX4.MDL.all = 0x9555AAA4;
ECanaMboxes.MBOX4.MDH.all = 0x89ABCDEF;
ECanaMboxes.MBOX5.MDL.all = 0x9555AAA5;
ECanaMboxes.MBOX5.MDH.all = 0x89ABCDEF;
ECanaMboxes.MBOX6.MDL.all = 0x9555AAA6;
ECanaMboxes.MBOX6.MDH.all = 0x89ABCDEF;
ECanaMboxes.MBOX7.MDL.all = 0x9555AAA7;
ECanaMboxes.MBOX7.MDH.all = 0x89ABCDEF;
ECanaMboxes.MBOX8.MDL.all = 0x9555AAA8;
ECanaMboxes.MBOX8.MDH.all = 0x89ABCDEF;
ECanaMboxes.MBOX9.MDL.all = 0x9555AAA9;
ECanaMboxes.MBOX9.MDH.all = 0x89ABCDEF;
ECanaMboxes.MBOX10.MDL.all = 0x9555AAAA;
ECanaMboxes.MBOX10.MDH.all = 0x89ABCDEF;
ECanaMboxes.MBOX11.MDL.all = 0x9555AAAB;
ECanaMboxes.MBOX11.MDH.all = 0x89ABCDEF;
ECanaMboxes.MBOX12.MDL.all = 0x9555AAAC;
ECanaMboxes.MBOX12.MDH.all = 0x89ABCDEF;
ECanaMboxes.MBOX13.MDL.all = 0x9555AAAD;
ECanaMboxes.MBOX13.MDH.all = 0x89ABCDEF;
ECanaMboxes.MBOX14.MDL.all = 0x9555AAAE;
ECanaMboxes.MBOX14.MDH.all = 0x89ABCDEF;
ECanaMboxes.MBOX15.MDL.all = 0x9555AAAF;
ECanaMboxes.MBOX15.MDH.all = 0x89ABCDEF;
/* Configure CAN interrupts */
//ECanaShadow.CANMIL.all = 0xFFFFFFFF ; // Interrupts asserted on eCAN1INT
ECanaShadow.CANMIL.all = 0x00000000 ; // Interrupts asserted on eCAN0INT
ECanaRegs.CANMIL.all = ECanaShadow.CANMIL.all;
ECanaShadow.CANMIM.all = 0xFFFFFFFF; // Enable interrupts for all mailboxes
ECanaRegs.CANMIM.all = ECanaShadow.CANMIM.all;
ECanaShadow.CANGIM.all = 0;
ECanaShadow.CANGIM.bit.I0EN = 1; // Enable eCAN1INT or eCAN0INT
ECanaShadow.CANGIM.bit.I1EN = 1;
ECanaRegs.CANGIM.all = ECanaShadow.CANGIM.all;
/* Reassign ISRs. i.e. reassign the PIE vector for ECAN0INTA_ISR and ECAN0INTA_ISR
to point to a different ISR than the shell routine found in DSP28_DefaultIsr.c.
This is done if the user does not want to use the shell ISR routine but instead
wants to embed the ISR in this file itself. */
PieVectTable.ECAN0INTA = &eCAN0INT_ISR;
PieVectTable.ECAN1INTA = &eCAN1INT_ISR;
/* Configure PIE interrupts */
PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable vector fetching from PIE block
PieCtrlRegs.PIEACK.bit.ACK9 = 1; // Enables PIE to drive a pulse into the CPU
// The interrupt can be asserted in either of the eCAN interrupt lines
// Comment out the unwanted line...
PieCtrlRegs.PIEIER9.bit.INTx5 = 1; // Enable INTx.5 of INT9 (eCAN0INT)
PieCtrlRegs.PIEIER9.bit.INTx6 = 1; // Enable INTx.6 of INT9 (eCAN1INT)
/* Configure system interrupts */
IER |= 0x0100; // Enable INT9 of CPU
EINT;
/* Begin transmitting */
ECanaRegs.CANTA.all = 0xFFFFFFFF; // Clear all "set" TAn bits, if any
ECanaRegs.CANTRS.all = 0xFFFFFFFF; // Set TRS for all mailboxes
while(ECanaRegs.CANTA.all != 0xFFFFFFFF) {}
}
/* --------------------------------------------------- */
/* ISR for PIE INT9.5 */
/* Connected to HECC0-INTA eCAN */
/* ----------------------------------------------------*/
interrupt void eCAN0INT_ISR(void)
{
ECanaShadow.CANTA.all = 0 ;
//ECanaRegs.CANTA.all = ECanaShadow.CANTA.all ;
int0count++;
PieCtrlRegs.PIEACK.bit.ACK9 = 1; // Enables PIE to drive a pulse into the CPU
IER |= 0x0100; // Enable INT9
EINT;
return;
}
/* --------------------------------------------------- */
/* ISR for PIE INT9.6 */
/* Connected to HECC1-INTA eCAN */
/* ----------------------------------------------------*/
interrupt void eCAN1INT_ISR(void)
{
asm (" NOP");
MIV = ECanaRegs.CANGIF1.bit.MIV1;
switch(MIV)
{
case 31:
ECanaShadow.CANTA.all = 0;
ECanaShadow.CANTA.bit.TA31 = 1;
ECanaRegs.CANTA.all = ECanaShadow.CANTA.all ;
break;
case 30:
ECanaShadow.CANTA.all = 0;
ECanaShadow.CANTA.bit.TA30 = 1;
ECanaRegs.CANTA.all = ECanaShadow.CANTA.all ;
break;
case 29:
ECanaShadow.CANTA.all = 0;
ECanaShadow.CANTA.bit.TA29 = 1;
ECanaRegs.CANTA.all = ECanaShadow.CANTA.all ;
break;
case 28:
ECanaShadow.CANTA.all = 0;
ECanaShadow.CANTA.bit.TA28 = 1;
ECanaRegs.CANTA.all = ECanaShadow.CANTA.all ;
break;
case 27:
ECanaShadow.CANTA.all = 0;
ECanaShadow.CANTA.bit.TA27 = 1;
ECanaRegs.CANTA.all = ECanaShadow.CANTA.all ;
break;
case 26:
ECanaShadow.CANTA.all = 0;
ECanaShadow.CANTA.bit.TA26 = 1;
ECanaRegs.CANTA.all = ECanaShadow.CANTA.all ;
break;
}
// ECanaShadow.CANTA.all = ECanaRegs.CANTA.all ;
int1count++;
PieCtrlRegs.PIEACK.bit.ACK9 = 1; // Enables PIE to drive a pulse into the CPU
IER |= 0x0100; // Enable INT9
EINT;
return;
}