Hi,
on F28335 I have observed that when I mix access to internal SARAM (L7) and SRAM on XINTF, the code executes substantially slower than when all accesses are on internal memory. This is also valid for part of code that exclusively manipulates SARAM data if it is preceded and followed by accesses to external memory. I'm guessing this has something to do with emptying the pipeline before switching memory but I would like to get a confirmation for my theory. Tried looking for an explanation in the documentation, but with no success.
Am I right in my guesses or something else is going on?
Regards,
Josip