This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SCI Transmit Motorware Libaries With TI RTOS

Hi,

I am having issues disabling SCI TX ISR after my intended messages have been transmitted. I have read on the forums on how to handle this. The following is my SCIB TX ISR code including TX disable and clearing TX FIFO functions:

void uartB_isr_tx(void)
{
	SCI_putDataBlocking(halHandle->sciBHandle, ack[0]);
	SCI_putDataBlocking(halHandle->sciBHandle, ack[1]);
	SCI_putDataBlocking(halHandle->sciBHandle, ack[2]);
	SCI_putDataBlocking(halHandle->sciBHandle, ack[3]);

	while(SCI_getTxFifoStatus(halHandle->sciBHandle) != SCI_FifoStatus_Empty);

	SCI_disableTxInt(halHandle->sciBHandle);
	SCI_clearTxFifoInt(halHandle->sciBHandle);
}
void SCI_disableTxInt(SCI_Handle sciHandle)
{
  SCI_Obj *sci = (SCI_Obj *)sciHandle;


  // clear the bits
  sci->SCICTL2 &= (~SCI_SCICTL2_TX_INT_ENA_BITS);

  return;
} // end of SCI_disableTxInt() function
void SCI_clearTxFifoInt(SCI_Handle sciHandle)
{
  SCI_Obj *sci = (SCI_Obj *)sciHandle;


  // set the bits
  sci->SCIFFTX |= SCI_SCIFFTX_INTCLR_BITS;

  return;
} // end of SCI_clearTxFifoInt() function

There wasn't a need to handle the PIE Registers since TI RTOS should be handling that.

Unfortunately I am unable to shut down the SCIB TX ISR and it continuously loops within it, and sending an endless stream of data. Does anyone know how to properly turn off the ISR once the intended message has been sent while using TI RTOS? I have tried disabling SCI TX all together but at times that has unintended behavior such as sending one more data set than it should.

Thanks!

Thanks!

  • Hi Nolan,

    What is your FFIL (FIFO interrupt level)? I am assuming you enabled the FIFO enhancement, is that correct?

    You are disabling the TXINT when in Non-FIFO mode in register SCICTL2. You need to disable the FIFO interrupt if you are using the FIFO. This is bit TXFFIENA in SCIFFTX.

    sal