Concerto - Analog and digital power and ground

Hi Etai,

The internal reference error is rolled into the datasheet spec' for gain error with internal reference.

As far as separating the ground planes, I would recommend that you do this if possible. However, the biggest consideration should be on providing good return paths for both your analog and digital signals when doing PCB layout and routing. One training on PCB layout I took actually recommend that you split off the ADC/Analog ground plane from the digital portion of the board, do your routing, then remove cuts in the plane.

Follow up to Etai's original question from the customer:

It looks like the eval board separates the 3.3V VDDIO power pins into various sections and ties them to the 3.3V power plane via a number of ferrite beads. I have never seen anything like this before and I don’t see any reference to how they are divided up or the need to do this in the datasheet. Page 120 of the datasheet lists the VDDIO pins but doesn’t even tell which ones are for USB or OSC. Can you confirm whether they should be connected to a plane with bypass caps located at the pins or all separated from the plane with ferrite beads as in the eval board?

Also, page 45 of the datasheet has diagrams of how to connect a 3.3V oscillator but it seems like the text on the following page contradicts the diagram. The bottom left diagram shows VSSosc as a no-connect but the text says, “In this case, the external oscillator should be grounded only through the VSSOSC pin.” Is VSSOSC internally connected to Vss? Which should I follow?

can’t find a spec for the input capacitance of the X1 pin. That is an important parameter for choosing an oscillator.

Hello Phong Le,

Are you using the F28M36 controlCARD? Following the DS recommendations is a minimum requirement for board design (VDDIO decoupling caps to VSS plane next to pins). The eval boards are designed by our experts and generally incorporate PCB best practices. The eval boards can be used as a good reference board design.

As for the external oscillator, when using a XTAL or resonator, the VSSOSC must be used. When using a single-ended 3.3V oscillator it is not necessary to connect the VSSOSC pin. This text needs to be edited in the DS.

Best Regards,
Adam Dunhoft

Additonal question, thanks for the help thus far Adam:

What is the maximum input capacitance of the X1 pin? Page 132 of the datasheet lists the rise time, fall time, and duty cycle requirements but if I’m using an external single ended oscillator, I need to know the load capacitance to guarantee meeting these requirements.

It is only necessary to have the load capacitance spec when implementing a XTAL across X1 and X2 pins. This is to ensure the XTAL oscillates at the center frequency. With a single-ended oscillator, the XTAL circuit is tuned internally thus it does not require a load capacitance spec.

Best Regards,
Adam Dunhoft

Adam:

We are talking about a different capacitance. The rise and fall time of the external single ended oscillator depends on knowing the load capacitance at its output which is connected to the X1 pin. Typical load capacitance for CMOS is 15pF. HCMOS is higher. Some clock chips are spec’d above 15pF but the majority are only spec’d for a 15pF load. For example, the TI Ethernet PHY we are using (TLK110PT), has a typical input capacitance of 15pF but a max of 30pF.  In order to meet the required rise time, I had to do some searching to find a chip that could guarantee performance with up to the max load.

Does that make sense?

Any input?

Hi Phong Le,

Sorry for the delayed response. Yes, the F28M36x device is a CMOS process and will meet your load capacitance spec of 15pF.

Best Regards,
Adam Dunhoft

Additional input needed on the Ethernet Phy portion of the concerto board:

We’re using the Ethernet Phy (TLK110) that is on the Concerto control card for our custom board and I’m confused about the footprint. The datasheet does not mention a thermal pad except on the mechanical page which shows the PT package and indicates that it *may* be a thermally enhanced package. If I download the PT48 part symbol with UltraLibrarian, there is no thermal pad in the footprint. On the other hand, the eval board layout for the Concerto MCU and the eval board schematic for the  TLK110 both show a thermal pad ground connection for pin 49 of TLK110. Is there a thermal pad under the TLK110 chip or not?

Phong,

It looks like TLK110 extended temperature package has pin49 (thermal pad). Below post says it is not available on TLK110 package.

Regards,

Manoj

So to clarify:

Thermal pad is only existent on the "extended temp package" version of the TLK110? 

Is that package catalog available?

Phong,

It looks like initially there was plan to release higher temperature version of TLK110 part. But, that part was never released. So, the only TLK110 part available is without thermal pad.

Regards,
Manoj