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How long the SDFM data will be ready after FILRES?

Other Parts Discussed in Thread: AMC1305M25, CONTROLSUITE

Hello,

Currently I am using F28377S Sigma-Delta to sampling the current for motor control. I use PWM11 to synchronize reset the Filter periodic.

 

Configuration is as following:

Comparator Module: SINC3, OSR_32

Sinc Filter Module: SINC3, OSR_128

PWM11 Frequency: 100MHz

Sigma-Delta from PWM5: 20MHz

1.How long the SDFM data will be ready after FILRES? How to calculate?

2.The following formula is from the F2837xS TRM to calculate the Latency of Sinc Filter, what's the mean of Order of Sinc filter? What's the value in my configuration?

Thanks in advance.

Best Regards.

  • Jason,

    FILRES from PWM11 only goes to data filter 1 and data filter 2. It doesn't synchronize comparator. I hope you are aware of it.

    Based on the data filter settings:-

    Order of data filter = 3 (because of you are using Sinc3 filter)

    What is input control mode (mode0/1/2/3) settings?

    Also, which SD modulator are you using?

    Regards,

    Manoj

  • Hello Manoj,

    Thank you very much for your response.

    I use input control mode: Mode 0

    The SD modulator is AMC1305M25.

    Best Regards.
  • Jason,

    For your filter settings, here is the calculation for latency of data fitler.


    Modulator data rate = 20 Mhz

    DOSR = 128

    Filter type = 3

    Data rate of data filter = Modulator data rate / DOSR

              = 20 Mhz / 128

    = 156.3 Khz


    Latency of data filter = Order of data filter / Data rate of data filter
                                         = 3 / 156.3 Khz
                                         = 19.2 us


    Regards,

    Manoj

  • I had 2 follow-up questions to Jason's original post:

    1) After FILRES, do I only have to wait for the filter-latency time to read valid data, OR do I have to wait filter-latency + measurement-acquisition-time. From another app-note, the measurement-acquisition-time is approximately the OSR/clock-rate, or 6.4us using Jason's numbers above.

    2) What are the implications of NOT using FILRES? I know that FILRES does not affect the comparators, and I have a working application using FILRES, but from the latest 28377xD errata, using the comparators is unreliable if FILRES is also used. I am struggling a bit to get a non-FILRES-application working as well as my current FILRES-application.

    Thanks,

    Jim

  • Jim,

    1) After FILRES, you need to wait for latency of data filter + 5 SD-Cx clock cycles to read valid data as mentioned in TRM and errata
    2) You don't need to use FILRES if your application doesn't need it.
    As you said, FILRES doesn't affect SDFM comparator module. Can you specify which errata items specifies SDFM comparator is unreliable when FILRES is used?

    sdfm_filters_sync_cpu example in controlSuite shows the example of non-FILRES SDFM example.

    Regards,
    Manoj
  • Manoj,

    I got it somewhat working without using FILRES, but my noise floor is probably 3-times higher without using FILRES, so right now I am still using it.

    I mis-wrote about the errata -- it was in the latest technical reference, In section 13.5 Data Filter Unit, it states:

    SDFM Comparator interrupts (IELx and IEHx) should be enabled only after providing sufficient settling time to make sure the comparator filter does not trip on these incorrect samples. Therefore, SDFM comparator interrupts (IELx and IEHx) should be enabled only after a sufficient delay is provided after the comparator filter is configured. This sufficient delay is calculated by adding the latency of the comparator filter and five SD-Cx clock cycles.

     In case of the SDFM data filter, each time the filter is enabled or reconfigured, or the filter is reset by the PWM sync pulse, or the filter is reset by SDDFPARMx.FEN, depending upon the filter type, there will be some incorrect samples as mentioned in Table 13-4.

     I read this as – because we are resetting the filter with the PWM sync pulse, there are known bad samples that can cause the comparator (over-current) to trip. I either have to figure out how to run without resetting the filter, or we cannot reliably use the SD comparators for over-current detection.

     Jim

  • Manoj et al,

    Can you respond with your opinion about my interpretation of the technical reference (in the last post)? As I interpreted the manual, I cannot use FILRES AND use the sigma-delta comparators for over-current detection, because using the PWM sync pulse to reset the filters can cause known bad samples to trip the comparators.

    I am hoping I have misinterpreted this section, because not using the comparators for over-current detection is really losing an important feature of this peripheral.

    Thanks,

    Jim

  • Jim,

    Below comment applies only when SDFM comparator is enabled for the 1st time and not when FILRES is reset. As I said before FILRES doesn't affect SDFM comparator in any way. The known bad samples apply only for data filter when the filter is reset by FILRES signal.

    SDFM Comparator interrupts (IELx and IEHx) should be enabled only after providing sufficient settling time to make sure the comparator filter does not trip on these incorrect samples. Therefore, SDFM comparator interrupts (IELx and IEHx) should be enabled only after a sufficient delay is provided after the comparator filter is configured. This sufficient delay is calculated by adding the latency of the comparator filter and five SD-Cx clock cycles.


    Regards,

    Manoj