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Equation for Modulator Gain in PFC

Other Parts Discussed in Thread: TMS320F28335

In analog control circuits, I've always calculated the low frequency gain of the modulator in a buck topology as the input voltage divided by the peak of the sawtooth.  For a boost I think the low frequency gain is the output voltage divided by the peak of the sawtooth (which I think is more of an approximation).

Since a PFC circuit is a boost topology with an inherent inner current loop and with a changing input voltage, how do you determine the low frequency gain of the modulator?  How can you properly compensate the outer voltage loop of you do not know the low frequency gain?

Also, I'm performing digital control of power supplies with a TMS320F28335.  If I want to control a buck converter, and I use the input voltage divided by the peak of the sawtooth to determine the low frequency gain, what amplitude do I use for the sawtooth?  I assume it is 1 volt, but this gives me a tremendous amount of gain for the 350 VDC power supply that I'm controlling.

  • For PFC current loop design you have to assume the input voltage as constant, then analyze the converter as an average current mode control dc-dc boost circuit and calculate your controller coefficients.

    This is valid since the bandwidth of the current loop is always at least a few kHz or more. Therefore, with respect to this fast current loop, the low frequency variation (120Hz) in the modulator can be considered very slow, i.e., almost a constant level. Then you can define the modulator gain as explained in the TI application reports "spra902a" (page 8) and "spraab3" (page 4).

    Shamim

  • Thank you for your quick reply.  

    I realize that you have a thorough understanding of this technique, but I unfortunately do not.  There are many steps left out.  I'm really not sure how you got the equation for GVC on page 8.  Should it be intuitive?  Perhaps if I spend enough time on it I can figure it out, but I'll try to work with my approach first.  I generate the compensation circuit in terms of s, then use the Bilinear transform to generate my discrete time coefficients.  I'll know in a couple of weeks how well it turns out.

    Regardless of the implementation, perhaps you can enlighten me on the big picture control.  I have a working simulation of a PFC circuit.  When I slow the voltage loop down (as recommended by everything that I've read) to have a 20Hz bandwidth, it does not respond well to step changes in load.  When I step the load on the output from 10% to 100%, the output cap will discharge before the voltage loop can respond to maintain regulation.  It's a high power system - 37 KW with a 26mF output capacitor, which proportionally is comparable to an example that I've seen of an 875W system with a 300uF.  There is obviously a strong relation between peak input voltage, output voltage, output capacitor, load current, and required bandwidth...which your GVC equation probably accounts for.

    Maybe if you could answer the following specific questions, I can figure out how to compensate my loops:

    1.  Will your system maintain regulation with a 10% to 100% step change in load?

    2. Is there significant overshoot of output voltage with a 100% to 10% step change in load?

  • Since the PFC voltage loop is designed to be very slow (10Hz~20Hz, as you mentioned) you can have high overshoot and undershoot under load transient. This gets corrected slowly and the output voltage reaches steady-state after several cycles (line cycles). So, yes, my system can take 10~100% load step. We also use non-linear voltage loop for better control of transient. What this does is under transient the voltage controller switches to a much higher bandwidth compensator and returns to normal low bandwidth compensator under steady-state. This way the PF is good during steady-state (with the low BW controller). Under transient the PF will be affected (because of higher BW controller) but that should be ok for that short duration..

    Shamim