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TMS320F28335PGFA, Rev: Issues with reading and writing to flash chip using XINTF

Guru 19925 points
Other Parts Discussed in Thread: TMS320F28335

Hello,

I have not been able to reliably read and write to a flash chip using the XINTF (16-bus).  

The code is attached and is a a modified version of the Example_2833xDMA_xintf_to_ram (i.e. example from control suit). I am using the XDS100v2 debugger to debug the code.  

I believe one of the issues is the the flash chip select low time.  The flash chip select is only staying low for approximately 40ns, which is significantly less than what it should be as specified by the following settings (from code):

    XintfRegs.XTIMING7.bit.XWRLEAD = 5;
    XintfRegs.XTIMING7.bit.XWRACTIVE = 12;
    XintfRegs.XTIMING7.bit.XWRTRAIL = 4;
    // Zone read timing
    XintfRegs.XTIMING7.bit.XRDLEAD = 5;
    XintfRegs.XTIMING7.bit.XRDACTIVE = 12;
    XintfRegs.XTIMING7.bit.XRDTRAIL = 4;

Could someone at TI please verify the code is working properly.

dma_xintf_to_ram.zip

Thanks,

Stephen

Updated: the previously attached project builds with errors

New Project (builds without errors):

0652.dma_xintf_to_ram.zip

  • Hello,

    Is anyone at TI working on this issue?

    Do you need anymore information?

    Thanks,

    Stephen

  • Hi Stephen,

    Did you check the time wrt no of XCLKOUT cycles? In another post you mentioned that XCLKOUT has some impact on the XINTF signal. Is this same setup or different one?

    Regards,

    Vivek Singh

  • Hello Vivek,

    It's the same setup.

    The number of XCLKOUT cycles  times the XCLKOUT frequency is matching the amount of time the chip select is low.

    The problem is that the chip select low time doesn't match the lead/active/trail setting.  

    Also, I decreased the active setting value by 1/2 for both read and write  (from 12 to 6) and the chip select low time went from 40ns to 51ns, which is odd since it should decrease and not increase.

    Stephen

  • Hello Vivek,

    I reduced the SYSCLK to 30MHz.  The chip select low time for various settings (Both write and read) are shown in the table below.

    Stephen

  • Hello Vivek,

    I failed to completely read the datasheet.  The setting range for lead,active and trail periods are shown below.

    My settings were overflowing the bit field.

    I'll try some correct settings and then get back with you with the results.

    Stephen

    XRDLEAD: 0 to 3.

    XRDACTIVE:  0 to 7

    XRDTRAIL: 0 to 3

    XWRLEAD: 0 to 3.

    XwRACTIVE:  0 to 7

    XWRTRAIL: 0 to 3

  • Ok, great. It's always good to check the value in registers via register view in CCS (or Memory window) to make sure the configuration values are as expected.

    Hope once you change the configuration, it'll work as expected.

    Regards,

    Vivek Singh

  • Hello Vivek,

    I replaced the flash (S29JL032J) and the uC (TMS320F28335) on the board and the flash read/writes are still intermittent.

    Debugging the board I am using requires two people (one to hold the probes on some vias and one to run the code).  There's no one available to help me right now, so I am hoping that I can determine what is causing the issue without probing too many XINTF lines on the board.

    The development board only has the following components:

    1. S29JL032J flash chip

    2. TMS320F28335 microcontroller

    3. CAN chip

    4. 1.8V,1.9V,3.3V and 1.0V switching regulators.

    5. filter Capacitor and inductors for above components.

    6. Two LEDs

    The attached code is being used to test the flash. 

    What strange is that in the CFI test part of the code, the first 200 to 800

    2063.Example_2833xDMA_xintf_to_flash2.c
    //###########################################################################
    // Description:
    //! \addtogroup f2833x_example_list
    //! <h1> DMA XINTF to RAM (dma_xintf_to_ram)</h1>
    //!
    //! This example will perform a block copy of 1024 words from Zone 7 XINTF (DMABuf2)
    //! to L4 SARAM (DMABuf1) .
    //! Transfer will be started by Timer0.
    //! We will use 32-bit DMA datasize.  Note this is independent from the XINTF
    //! data width which is x16.
    //!
    //! \b Watch \b Variables \n
    //! - DMABuf1
    //! - DMABuf2
    //
    //
    //###########################################################################
    // $TI Release: F2833x/F2823x Header Files and Peripheral Examples V140 $
    // $Release Date: March  4, 2015 $
    // $Copyright: Copyright (C) 2007-2015 Texas Instruments Incorporated -
    //             http://www.ti.com/ ALL RIGHTS RESERVED $
    //###########################################################################
    
    #include "DSP28x_Project.h"     // Device Headerfile and Examples Include File
    #include "S29JLxxxJ.h"
    
    void init_zone7(void);
    
    #define FLASH_BASE_ADDRESS  0x00200000UL
    
    Uint16 u16flashReadValue = 0;
    Uint32 u32address;
    
    Uint16 u16ArrayData[10] =
    { 0x1234, 0x1355, 0x1866, 0x9103, 0x9384, 0x8510, 0x1029, 0x9876, 0x5643, 1523 };
    Uint16 m = 0;
    
    // Defined in linker cmd file
    extern unsigned int ramfuncs_loadstart;
    extern unsigned int ramfuncs_loadsize;
    extern unsigned int ramfuncs_runstart;
    
    void TurnONLED1(void);
    void TurnOFFLED1(void);
    void TurnONLED2(void);
    void TurnOFFLED2(void);
    
    DEVSTATUS writeStatus;
    
    Uint32 count1 = 0;
    Uint32 count2 = 0;
    Uint32 count3 = 0;
    Uint32 count4 = 0;
    Uint32 count5 = 0;
    Uint32 count6 = 0;
    Uint32 count7 = 0;
    Uint32 count8 = 0;
    Uint32 count9 = 0;
    Uint32 count10 = 0;
    Uint32 count11 = 0;
    Uint32 countTotal = 0;
    Uint32 count[10];
    unsigned int bDoCFIcmds = 1;
    unsigned int bDoWriteData = 1;
    unsigned int bDoReadData = 1;
    
    #define SECONDS_TO_MICROSECONDS(x) (Uint32)(x*1000.0*1000.0)
    Uint32 TimeDelay = SECONDS_TO_MICROSECONDS(6.0);
    
    void main(void)
    {
        Uint16 i;
        Uint32 j, k;
    
        if (!(SysCtrlRegs.WDCR & 0x0080))  //check WDFLag
        {
            EALLOW;
            SysCtrlRegs.SCSR |= 0x0001;
            SysCtrlRegs.WDCR = 0x0007;
            EDIS;
    
            while (1)
            {
            };
        }
    
        EALLOW;
        SysCtrlRegs.WDCR = 0x00E8;  //This will also disable the WDog
        EDIS;
    
        memcpy(&ramfuncs_runstart, &ramfuncs_loadstart, (Uint32) &ramfuncs_loadsize);
    
        InitFlash();
    
    // Step 1. Initialize System Control:
    // PLL, WatchDog, enable Peripheral Clocks
    // This example function is found in the DSP2833x_SysCtrl.c file.
        InitSysCtrl();
    
        DSP28x_usDelay(5000000);
    
        TurnONLED2();
        TurnOFFLED1();
    
        //ReadBackRequest(10,5);
    
        //while(1){};
    
        init_zone7();
    
        u32address = 0x4200UL;
        //u32address = 0x0800UL;
        //u32address = 0x4390UL;
    
        ///////////////////////////////
        // TEST CFI
        ///////////////////////////////
        while (bDoCFIcmds)
        {
            countTotal++;
            u16flashReadValue = lld_ReadCfiWord((FLASHDATA*) FLASH_BASE_ADDRESS, (ADDRESS) 0x0010);
            if (u16flashReadValue != 0x0051)
            {
                count1++;
            }
            u16flashReadValue = lld_ReadCfiWord((FLASHDATA*) FLASH_BASE_ADDRESS, (ADDRESS) 0x0011);
            if (u16flashReadValue != 0x0052)
            {
                count2++;
            }
            u16flashReadValue = lld_ReadCfiWord((FLASHDATA*) FLASH_BASE_ADDRESS, (ADDRESS) 0x0012);
            if (u16flashReadValue != 0x0059)
            {
                count3++;
            }
            u16flashReadValue = lld_ReadCfiWord((FLASHDATA*) FLASH_BASE_ADDRESS, (ADDRESS) 0x0013);
            if (u16flashReadValue != 0x0002)
            {
                count4++;
            }
            u16flashReadValue = lld_ReadCfiWord((FLASHDATA*) FLASH_BASE_ADDRESS, (ADDRESS) 0x0014);
            if (u16flashReadValue != 0x0000)
            {
                count5++;
            }
            u16flashReadValue = lld_ReadCfiWord((FLASHDATA*) FLASH_BASE_ADDRESS, (ADDRESS) 0x0015);
    
            if (u16flashReadValue != 0x0040)
            {
                count6++;
            }
            u16flashReadValue = lld_ReadCfiWord((FLASHDATA*) FLASH_BASE_ADDRESS, (ADDRESS) 0x0016);
            if (u16flashReadValue != 0x0000)
            {
                count7++;
            }
            u16flashReadValue = lld_ReadCfiWord((FLASHDATA*) FLASH_BASE_ADDRESS, (ADDRESS) 0x0017);
            if (u16flashReadValue != 0x0000)
            {
                count8++;
            }
            u16flashReadValue = lld_ReadCfiWord((FLASHDATA*) FLASH_BASE_ADDRESS, (ADDRESS) 0x0018);
            if (u16flashReadValue != 0x0000)
            {
                count9++;
            }
            u16flashReadValue = lld_ReadCfiWord((FLASHDATA*) FLASH_BASE_ADDRESS, (ADDRESS) 0x0019);
            if (u16flashReadValue != 0x0000)
            {
                count10++;
            }
            u16flashReadValue = lld_ReadCfiWord((FLASHDATA*) FLASH_BASE_ADDRESS, (ADDRESS) 0x001A);
            if (u16flashReadValue != 0x0000)
            {
                count11++;
            }
        }
    
        ///////////////////////////////
        // TEST Flash Writes
        ///////////////////////////////
        writeStatus = DEV_NOT_BUSY;
        while (bDoWriteData)
        {
            for (i = 0; i < 10; i++)
            {
                do
                {
                    writeStatus = lld_ProgramOp((FLASHDATA *) FLASH_BASE_ADDRESS, (ADDRESS) (u32address + (Uint32) (2UL * i)), (FLASHDATA) u16ArrayData[i]);
                } while (DEV_VERIFY_ERROR == writeStatus);
    
                u16flashReadValue = lld_ReadOp((FLASHDATA *) FLASH_BASE_ADDRESS, (ADDRESS) (u32address + (Uint32) (2UL * i)));
    
            }
        }
    
        ///////////////////////////////
        // TEST Flash reads
        ///////////////////////////////
        while (bDoReadData)
        {
            for (j = 0; j < 80000U; j++)
            {
                for (i = 0; i < 10; i++)
                {
                    countTotal++;
                    u16flashReadValue = lld_ReadOp((FLASHDATA *) FLASH_BASE_ADDRESS, (ADDRESS) (u32address + (Uint32) (2UL * i)));
                    //u16flashReadValue = (*(( (volatile unsigned short*)(FLASH_BASE_ADDRESS) ) + (u32address+i*2UL)));
                    //pu16flashAddress = (volatile unsigned short*)(FLASH_BASE_ADDRESS + u32address + i*2UL);
                    // u16flashReadValue = *pu16flashAddress;
                    if (u16flashReadValue != u16ArrayData[i])
                    {
                        count[i]++;
                    }
                }
            }
        }
    
        TurnONLED1();
    
        while (1)
        {
        };
    }
    
    // Configure the timing parameters for Zone 7.
    // Notes:
    //    This function should not be executed from XINTF
    //    Adjust the timing based on the data manual and
    //    external device requirements.
    void init_zone7(void)
    {
        EALLOW;
        // Make sure the XINTF clock is enabled
        SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1;
        EDIS;
    
        // Configure the GPIO for XINTF with a 16-bit data bus
        // This function is in DSP2833x_Xintf.c
        InitXintf16Gpio();
        EALLOW;
        // All Zones---------------------------------
        // Timing for all zones based on XTIMCLK = SYSCLKOUT
        XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
        // Buffer up to 3 writes
        XintfRegs.XINTCNF2.bit.WRBUFF = 3;
        // XCLKOUT is enabled
        XintfRegs.XINTCNF2.bit.CLKOFF = 0;
        // XCLKOUT = XTIMCLK
        XintfRegs.XINTCNF2.bit.CLKMODE = 0;
        // Disable XHOLD to prevent XINTF bus from going into high impedance state
        // whenever TZ3 signal goes low. This occurs because TZ3 on GPIO14 is
        // shared with HOLD of XINTF
        XintfRegs.XINTCNF2.bit.HOLD = 1;
    
        // Zone 7------------------------------------
        // When using ready, ACTIVE must be 1 or greater
        // Lead must always be 1 or greater
        // Zone write timing
        XintfRegs.XTIMING7.bit.XWRLEAD = 3;
        XintfRegs.XTIMING7.bit.XWRACTIVE = 7;
        XintfRegs.XTIMING7.bit.XWRTRAIL = 3;
        // Zone read timing
        XintfRegs.XTIMING7.bit.XRDLEAD = 3;
        XintfRegs.XTIMING7.bit.XRDACTIVE = 7;
        XintfRegs.XTIMING7.bit.XRDTRAIL = 3;
    
        // don't double all Zone read/write lead/active/trail timing
        XintfRegs.XTIMING7.bit.X2TIMING = 0;
    
        // Zone will not sample XREADY signal
        XintfRegs.XTIMING7.bit.USEREADY = 0;
        XintfRegs.XTIMING7.bit.READYMODE = 0;
    
        // 1,1 = x16 data bus
        // 0,1 = x32 data bus
        // other values are reserved
        XintfRegs.XTIMING7.bit.XSIZE = 3;
        EDIS;
    
        //Force a pipeline flush to ensure that the write to
        //the last register configured occurs before returning.
        __asm(" RPT #7 || NOP");
    }
    
    void TurnONLED1(void)
    {
        EALLOW;
        GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 0;
        GpioCtrlRegs.GPADIR.bit.GPIO12 = 1;
        GpioDataRegs.GPACLEAR.bit.GPIO12 = 1;
        EDIS;
    }
    
    void TurnOFFLED1(void)
    {
        EALLOW;
        GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 0;
        GpioCtrlRegs.GPADIR.bit.GPIO12 = 1;
        GpioDataRegs.GPASET.bit.GPIO12 = 1;
        EDIS;
    }
    
    void TurnONLED2(void)
    {
        EALLOW;
        GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 0;
        GpioCtrlRegs.GPADIR.bit.GPIO13 = 1;
        GpioDataRegs.GPACLEAR.bit.GPIO13 = 1;
        EDIS;
    }
    
    void TurnOFFLED2(void)
    {
        EALLOW;
        GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 0;
        GpioCtrlRegs.GPADIR.bit.GPIO13 = 1;
        GpioDataRegs.GPASET.bit.GPIO13 = 1;
        EDIS;
    }
    
    
    reads will be in error.  From that point onward, there are no more read errors for that specific test.  In other words, I could run it forever and there would be no read errors.  It doesn't happen that way for the flash read test situation.  For the flash read test, the read errors continue to occur.   

    Here is one set of results from the CFI test:

    count1=356
    count2=357
    count3=417
    count4=405
    count5=357
    count6=358
    count7=432
    count8=432
    count9=357
    count10=356
    countTotal=1835035

     Stephen