PWM_scheme.txt
else{ /* */\
/* State s1: current flows to motor windings from phase A->B, de-energized phase = C */\
if (v.CmtnPointer==0) /* */\
{ /* */\
EPwm1Regs.AQCSFRC.bit.CSFB = 2; /* Forcing a continuous High on output B of EPWM1 */\
EPwm1Regs.CMPA.half.CMPA = (int16)(Tmp>>15); /* PWM signal on output B of EPWM1 (Q15 -> Q0) */\
EPwm1Regs.AQCSFRC.bit.CSFA = 0; /* Forcing disabled on output A of EPWM1 */\
EPwm1Regs.AQCTLA.bit.CAU = 1; /* Set low when CTR = CMPA on UP-count */\
EPwm1Regs.AQCTLA.bit.ZRO = 2; /* Set high when CTR = Zero */\
/* */\
EPwm2Regs.AQCSFRC.bit.CSFA = 0; /* Forcing disabled on output A of EPWM2 */\
EPwm2Regs.AQCSFRC.bit.CSFB = 2; /* Forcing a continuous High on output B of EPWM2 */\
EPwm2Regs.AQCTLA.bit.CAU = 2; /* Set high when CTR = CMPA on UP-count */\
EPwm2Regs.AQCTLA.bit.ZRO = 1; /* Set low when CTR = Zero */\
EPwm2Regs.CMPA.half.CMPA = (int16)(Tmp>>15); /* PWM signal on output B of EPWM1 (Q15 -> Q0) */\
/* */\
EPwm3Regs.AQCSFRC.bit.CSFA = 1; /* Forcing a continuous Low on output A of EPWM3 */\
EPwm3Regs.AQCSFRC.bit.CSFB = 1; /* Forcing a continuous Low on output B of EPWM3 */\
} /* */\
/* */\
/* State s2: current flows to motor windings from phase A->C, de-energized phase = B */\
else if (v.CmtnPointer==1) /* */\
{ /* */\
EPwm1Regs.AQCSFRC.bit.CSFB = 2; /* Forcing a continuous High on output B of EPWM1 */\
EPwm1Regs.CMPA.half.CMPA = (int16)(Tmp>>15); /* PWM signal on output B of EPWM1 (Q15 -> Q0) */\
EPwm1Regs.AQCSFRC.bit.CSFA = 0; /* Forcing disabled on output A of EPWM1 */\
EPwm1Regs.AQCTLA.bit.CAU = 1; /* Set low when CTR = CMPA on UP-count */\
EPwm1Regs.AQCTLA.bit.ZRO = 2; /* Set high when CTR = Zero */\
/* */\
EPwm2Regs.AQCSFRC.bit.CSFA = 1; /* Forcing a continuous Low on output A of EPWM2 */\
EPwm2Regs.AQCSFRC.bit.CSFB = 1; /* Forcing a continuous Low on output B of EPWM2 */\
/* */\
EPwm3Regs.AQCSFRC.bit.CSFB = 2; /* Forcing a continuous High on output A of EPWM3 */\
EPwm3Regs.AQCSFRC.bit.CSFA = 0; /* Forcing disabled on output B of EPWM3 */\
EPwm3Regs.AQCTLA.bit.CAU = 2; /* Set high when CTR = CMPA on UP-count */\
EPwm3Regs.AQCTLA.bit.ZRO = 1; /* Set low when CTR = Zero */\
EPwm3Regs.CMPA.half.CMPA = (int16)(Tmp>>15); /* PWM signal on output B of EPWM1 (Q15 -> Q0) */\
} /* */\
/* */\
/* State s3: current flows to motor windings from phase B->C, de-energized phase = A */\
else if (v.CmtnPointer==2) /* */\
{ /* */\
EPwm1Regs.AQCSFRC.bit.CSFA = 1; /* Forcing a continuous Low on output A of EPWM1 */\
EPwm1Regs.AQCSFRC.bit.CSFB = 1; /* Forcing a continuous Low on output B of EPWM1 */\
/* */\
EPwm2Regs.AQCSFRC.bit.CSFB = 2; /* Forcing a continuous High on output B of EPWM2 */\
EPwm2Regs.CMPA.half.CMPA = (int16)(Tmp>>15); /* PWM signal on output B of EPWM2 (Q15 -> Q0) */\
EPwm2Regs.AQCSFRC.bit.CSFA = 0; /* Forcing disabled on output A of EPWM2 */\
EPwm2Regs.AQCTLA.bit.CAU = 1; /* Set low when CTR = CMPA on UP-count */\
EPwm2Regs.AQCTLA.bit.ZRO = 2; /* Set high when CTR = Zero */\
/* */\
EPwm3Regs.AQCSFRC.bit.CSFA = 0; /* Forcing disabled on output A of EPWM3 */\
EPwm3Regs.AQCSFRC.bit.CSFB = 2; /* Forcing a continuous High on output B of EPWM3 */\
EPwm3Regs.AQCTLA.bit.CAU = 2; /* Set high when CTR = CMPA on UP-count */\
EPwm3Regs.AQCTLA.bit.ZRO = 1; /* Set low when CTR = Zero */\
EPwm3Regs.CMPA.half.CMPA = (int16)(Tmp>>15); /* PWM signal on output B of EPWM1 (Q15 -> Q0) */\
} /* */\
/* */\
/* State s4: current flows to motor windings from phase B->A, de-energized phase = C */\
else if (v.CmtnPointer==3) /* */\
{ /* */\
EPwm1Regs.AQCSFRC.bit.CSFB = 2; /* Forcing a continuous High on output B of EPWM1 */\
EPwm1Regs.AQCSFRC.bit.CSFA = 0; /* Forcing disabled on output A of EPWM1 */\
EPwm1Regs.AQCTLA.bit.CAU = 2; /* Set high when CTR = CMPA on UP-count */\
EPwm1Regs.AQCTLA.bit.ZRO = 1; /* Set low when CTR = Zero */\
EPwm1Regs.CMPA.half.CMPA = (int16)(Tmp>>15); /* PWM signal on output B of EPWM1 (Q15 -> Q0) */\
/* */\
EPwm2Regs.AQCSFRC.bit.CSFB = 2; /* Forcing a continuous High on output B of EPWM2 */\
EPwm2Regs.CMPA.half.CMPA = (int16)(Tmp>>15); /* PWM signal on output B of EPWM2 (Q15 -> Q0) */\
EPwm2Regs.AQCSFRC.bit.CSFA = 0; /* Forcing disabled on output A of EPWM2 */\
EPwm2Regs.AQCTLA.bit.CAU = 1; /* Set low when CTR = CMPA on UP-count */\
EPwm2Regs.AQCTLA.bit.ZRO = 2; /* Set high when CTR = Zero */\
/* */\
EPwm3Regs.AQCSFRC.bit.CSFA = 1; /* Forcing a continuous Low on output A of EPWM3 */\
EPwm3Regs.AQCSFRC.bit.CSFB = 1; /* Forcing a continuous Low on output B of EPWM3 */\
} /* */\
/* */\
/* State s5: current flows to motor windings from phase C->A, de-energized phase = B */\
else if (v.CmtnPointer==4) /* */\
{ /* */\
EPwm1Regs.AQCSFRC.bit.CSFB = 2; /* Forcing a continuous High on output A of EPWM1 */\
EPwm1Regs.AQCSFRC.bit.CSFA = 0; /* Forcing disabled on output B of EPWM1 */\
EPwm1Regs.AQCTLA.bit.CAU = 2; /* Set high when CTR = CMPA on UP-count */\
EPwm1Regs.AQCTLA.bit.ZRO = 1; /* Set low when CTR = Zero */\
EPwm1Regs.CMPA.half.CMPA = (int16)(Tmp>>15); /* PWM signal on output B of EPWM1 (Q15 -> Q0) */\
/* */\
EPwm2Regs.AQCSFRC.bit.CSFA = 1; /* Forcing a continuous Low on output A of EPWM2 */\
EPwm2Regs.AQCSFRC.bit.CSFB = 1; /* Forcing a continuous Low on output B of EPWM2 */\
/* */\
EPwm3Regs.AQCSFRC.bit.CSFB = 2; /* Forcing a continuous High on output B of EPWM3 */\
EPwm3Regs.CMPA.half.CMPA = (int16)(Tmp>>15); /* PWM signal on output B of EPWM3 (Q15 -> Q0) */\
EPwm3Regs.AQCSFRC.bit.CSFA = 0; /* Forcing disabled on output A of EPWM3 */\
EPwm3Regs.AQCTLA.bit.CAU = 1; /* Set low when CTR = CMPA on UP-count */\
EPwm3Regs.AQCTLA.bit.ZRO = 2; /* Set high when CTR = Zero */\
} /* */\
/* */\
/* State s6: current flows to motor windings from phase C->B, de-energized phase = A */\
else if (v.CmtnPointer==5) /* */\
{ /* */\
EPwm1Regs.AQCSFRC.bit.CSFA = 1; /* Forcing a continuous Low on output A of EPWM1 */\
EPwm1Regs.AQCSFRC.bit.CSFB = 1; /* Forcing a continuous Low on output B of EPWM1 */\
/* */\
EPwm2Regs.AQCSFRC.bit.CSFB = 2; /* Forcing a continuous High on output B of EPWM2 */\
EPwm2Regs.AQCSFRC.bit.CSFA = 0; /* Forcing disabled on output B of EPWM2 */\
EPwm2Regs.AQCTLA.bit.CAU = 2; /* Set high when CTR = CMPA on UP-count */\
EPwm2Regs.AQCTLA.bit.ZRO = 1; /* Set low when CTR = Zero */\
EPwm2Regs.CMPA.half.CMPA = (int16)(Tmp>>15); /* PWM signal on output B of EPWM1 (Q15 -> Q0) */\
/* */\
EPwm3Regs.AQCSFRC.bit.CSFB = 2; /* Forcing a continuous High on output B of EPWM3 */\
EPwm3Regs.CMPA.half.CMPA = (int16)(Tmp>>15); /* PWM signal on output B of EPWM3 (Q15 -> Q0) */\
EPwm3Regs.AQCSFRC.bit.CSFA = 0; /* Forcing disabled on output A of EPWM3 */\
EPwm3Regs.AQCTLA.bit.CAU = 1; /* Set low when CTR = CMPA on UP-count */\
EPwm3Regs.AQCTLA.bit.ZRO = 2; /* Set high when CTR = Zero */\
} /* */\
} /* */\
#endif // __F2803X_BLDCPWM_H__
I am using DRV8312-C2 kit with the software BLDC_Sensored. I modified the bldcpwm_BLDC.h to follow the recommended complementary PWM scheme as described by the datasheet (refer to section 9.2.4).
Testing the code, I changed the DFuncDesired from initial of 3276 to final value of 14000. The measured speed decreased. I decreased the DFuncDesired from 14000 to 12000. The measured speed increased.
This is exactly opposite to what I expected. Increasing DFuncDesired should increase speed. Decreasing it should decrease the speed.
The DFuncDesired value should correlate to the PWM Duty Cycle (as seen with the original bldcpwm_BLDC.h). Using the recommended complementary PWM scheme (see attached portion of revised bldcpwm_BLDC.h), the DFuncDesired value correlates to when PWM = LOW.
How do I correct this? I want to use the recommended PWM scheme but the DFuncDesired value should correlate to the PWM Duty Cycle.
