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controlCARD for F28M36P63 suggests a strange power distribution network (isolated power pins)

Hello. I think a similar question was already discussed but not in as much detail as it would deserve.

We are designing a board that makes use of concerto F28M36P63C2ZWTT and we are facing a dilemma on what to do with Concerto's power supply pins. The F28M36x controlCARD (sch. v1.1 = latest) suggests a very strange PDN that, according to the modern practice, I think it doesn't sound right. Here you see (F28M36x controlCARD schematic attached) that:

a) On area 1 (VDD12.x and VDD18.x pins), controlCARD uses only one power pin, the rest are isolated from the former and connected to individual decoupling capacitors. I think that, even in the case of enabling of the internal regulator, the suggested layout is suboptimal: instead of so many discrete capacitor connections, it would be much easier to connect, e.g. the VDD12.x Concerto pins to a single area fill  that is directly connected to VDD_1V2 (while, of course, keeping the number of decoupling capacitors). This would have the additional benefit of lower connection inductance for all these capacitors (plane spread inductance instead of plain tracks).

b) On area 2 (VDDIO.x pins) , controlCARD splits the power pins into 8 groups, via ferrite beads. However, according to latest literature, this practice (i.e. the isolation of noisy loads) not only degrades PDN performance due to under-damping effects but it also does not make an improvement elsewhere since only the sensitive subcircuits need to be isolated (and not the noisy ones). Again I think it would be more effective, from the power integrity point of view, to use a signle area fill on all VDDIO pins, and entirely omit the ferrite beads (or, at least, keep only one of them for connecting VDD_3V3 to the aforementioned area fill).

In any case, I would be grateful to hear your suggestions on the matter.

Best regards,

Dimitrios

  • Hi Dimitrios,

    a) Areas 1: I agree with your analysis.  Early in this chip's development, we believed that it would be advantageous to separate each of the LDO output pins' capacitors because of the internal structure of the device.  About a year or so ago, we resolved that it would be more optimal to tie the pins together near the device (but keeping the capacitors). 

    Again, either way should be viable - the latter (which is what you have mentioned in your post) should be more optimal though. 

    Because a revision of the cCARD hardware may not occur, I believe it would be appropriate to mention this topic in the controlCARD's infosheet.  I will file a bug against this document so that the change is made at the next appropriate time.

    ===

    b) Area 2: the usage of ferrites can be controversial.  It can certainly be detrimental if done incorrectly - it can also improve things, like EMC, when done well. 

    I will admit that the C2000 group has not done significant testing with the bead filter usage on this design.  That being said, it has shown to be effective, as far as I am aware. 

    Your question revolves around what is optimal, and for that I will have to say that it depends on the full system.  Your analysis/suggestion is logical and likely holds some degree of merit.

    The device itself does not require ferrite bead filtering - the needs, especially on the VDDIO pins, is that the power supply be able to deliver the appropriate amount of current for the device (as described in the datasheet).  You are free to use the PDN you are most comfortable with in your design.


    Thank you,
    Brett

  • Hi Brett,

    Many thanks the prompt response. I always enjoy the level of support on these forums!

    Best regards,
    Dimitrios