Has anyone verified the BSDL file for the concerto (F28M35xnnx file: sprm558.bsd) in hardware?

Hi Knut,

There are some initialization needed for Concerto BSDL to work.

Can you check the value driven on EMU0 and EMU1 pins. To have this work correctly, EMU0 should have value '1' and EMU1 should have value '0' from power-up of the device.

Regards,

Vivek Singh

Vivek,

I added the states to the EMU0 and EMU1 pins as described.  Unfortunately there is no difference in the test performance.  Are there any other things I need to consider?

Thanks

Only other requirement is that TRSTn pins should be toggled from '0' -> '1' after device is powered up (XRSn is '1') which tool should take care. Could you check this as well.

Regards,
Vivek Singh

Vivek,

I toggled the TRSTn pin as you described with no change from previous test result.

Knut

Hi,

Is it possible for you to post the snapshot of the EMU0/EMU1/XRSN and TRSTn waveforms on scope?

Regards,

Vivek Singh

Vivek,

Requested scope pictures attached.

I also noticed the device ID bit stream is shifted by one bit.  If I add an additional clock cycle immediately before clocking out the ID bits, the correct bit stream is seen, however the IO pin test still fail.

Knut

Hi Knut, I don't see any pictures here. Could you upload the attachments again.

Regards,
Vivek Singh

I used the Edit/insert media button...Trying again...

Knut

Thanks Knut.

I can see these waveforms now and everything look good here. Let me discuss this with our team and I'll get back to you.

Regards,

Vivek Singh

Hi Knut,

In the TRSTn waveform snapshot, TRSTn pin goes from '0' -> '1' and then after some time it again goes to '0' and transition back to '1'. Why there is IInd transition? Id during run time TRSTn goes to '0' then it'll not work. Could you confirm this. Also was there any modification made in BSDL file?

Regards,
Vivek Singh

The actual test begins when the pulse on the lower trace goes high.  The initial low state of TRST is the "natural" state of the board before any test vectors are applied.  The clocks before TRST goes low again are because Agilent's software holds TMS high and applies 6 clocks which takes the TAP state machine to Test-Logic-Reset state.  This is done because not all TAPs have the TRST pin.  Taking TRST low does the same thing only asynchronously.  Keeping TRST high allows the TAP state machine to operate normally.

Knut

Thanks Knut !!

Keeping TRST high allows the TAP state machine to operate normally.

Does it mean the issue you were seeing is resolved and it's working fine now (after keeping TRST pin high)?

Regards,

Vivek ISngh

Absolutely not.  All previous issues remain.

Knut