Hi All,
The ADC module of a TMS320F28335 on an eZdsp borard seems to have too much gain. Using a slightly modified TI example, the ADC value is about 2570 for a 1 V input. This corresponds to saturation at about 1.6 V. I have found that the gain can be controlled using the 7 LSBs of ADCREFSEL. By changing these I can adjust the full-scale value between 1.8 V and 1.1 V. The largest value of 1.8 V is far away from the 3 V given in the ADC manual. Can anyone give some idea on what might be affecting the gain? Thanks for any assistance.
Jim Monte
#include "DSP28x_Project.h" #define N_AVG 10000 // Number of values to average #define BUF_SIZE 4 // Sample buffer size static void init_adc_custom_cal(void); main() { Uint16 i; Uint32 SampleTable[BUF_SIZE]; InitSysCtrl();// DSP2833x_SysCtrl.c file; PLL, Watchdog, Peripheral Clocks DINT;// Disable CPU interrupts InitPieCtrl();// DSP2833x_PieCtrl.c file IER = 0x0000;// Disable CPU interrupts IFR = 0x0000;// Clear all CPU interrupts InitPieVectTable();// DSP2833x_PieVect.c file //ADC setup for this example #if 1 init_adc_custom_cal();// DSP2833x_Adc.c file #else InitAdc(); #endif AdcRegs.ADCTRL1.bit.ACQ_PS = 0xF;// acquisition window size AdcRegs.ADCTRL1.bit.CPS = 0; AdcRegs.ADCTRL3.bit.ADCCLKPS = 1;// ADC clock = 75MHz/(2*3*(0+1))=12.5MHz AdcRegs.ADCTRL1.bit.SEQ_CASC = 1;// Cascaded mode AdcRegs.ADCTRL3.bit.SMODE_SEL = 0;// Sequential sampling mode AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 3; AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0;// ADC input channel: ADCINA0 AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 1;// ADC input channel: ADCINA0 AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 2;// ADC input channel: ADCINA0 AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 3;// ADC input channel: ADCINA0 AdcRegs.ADCTRL1.bit.CONT_RUN = 1;// Continuous conversion mode AdcRegs.ADCTRL2.all = 0x2000;// Start SEQ1; INT_SEQ1 is set at the end of every SEQ1 sequence for ( ; ; ) { for (i = 0; i < BUF_SIZE; i++) { SampleTable[i] = 0; } for (i = 0; i < N_AVG; i++) { while (AdcRegs.ADCST.bit.INT_SEQ1== 0) {} // Wait for interrupt AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; SampleTable[0] += AdcRegs.ADCRESULT0 >> 4; SampleTable[1] += AdcRegs.ADCRESULT1 >> 4; SampleTable[2] += AdcRegs.ADCRESULT2 >> 4; SampleTable[3] += AdcRegs.ADCRESULT3 >> 4; } SampleTable[0] /= N_AVG; SampleTable[1] /= N_AVG; SampleTable[2] /= N_AVG; SampleTable[3] /= N_AVG; } } static void init_adc_custom_cal(void) { extern void DSP28x_usDelay(Uint32 Count); // *IMPORTANT* // The ADC_cal function, which copies the ADC calibration values from TI reserved // OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs automatically in the // Boot ROM. If the boot ROM code is bypassed during the debug process, the // following function MUST be called for the ADC to function according // to specification. The clocks to the ADC MUST be enabled before calling this // function. // See the device data manual and/or the ADC Reference // Manual for more information. EALLOW; SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; /* Calibration */ #if 1 AdcRegs.ADCOFFTRIM.all = 505; /* 0:8, 505 from factory */ // AdcRegs.ADCREFSEL.all = 7490; /* 0:13, 7460 from factory */ AdcRegs.ADCREFSEL.all = 0x0000; /* 0:13, 7460 from factory */ #else asm(" MOVW DP, #0x711C >> 6"); asm(" MOV @28, #0x16383"); asm(" MOV @29, #0x511"); #endif EDIS; // To powerup the ADC the ADCENCLK bit should be set first to enable // clocks, followed by powering up the bandgap, reference circuitry, and ADC core. // Before the first conversion is performed a 5ms delay must be observed // after power up to give all analog circuits time to power up and settle // Please note that for the delay function below to operate correctly the // CPU_RATE define statement in the DSP2833x_Examples.h file must // contain the correct CPU clock period in nanoseconds. AdcRegs.ADCTRL3.all = 0x00E0; // Power up bandgap/reference/ADC circuits DELAY_US(5000L); // Delay before converting ADC channels return; } /* end of function init_adc_custom_cal */