I'm having trouble getting the ADC2 to sample on the eval card with docking station. I've set up the SOC for both ADC1 and ADC2 and I'm software forcing the SOC. I'm using SOC0-SOC5 on ADC1 and SOC0-SOC3 on ADC2. I'm interrupting after SOC5 finishes conversion. The interrupt is working and my ADC1 result registers are getting updated but the ADC2 registers are staying at zero. I thought the SOCX for ADC1 and ADC2 would both happen at the same time so when SOC5 finishes all of the conversions for both ADC1 and ADC2 would be finished. I tried interrupting instead on ADC2 SOC3 EOC but I'm getting the same results. I have a voltage that I want to sample connected to the B2 pin on the docking station. I'm trying to sample ADC2_A2 (from the schematics the B2 pin looks right but I tried all of the B pins on the docking station and that didn't change my results).
How come it's not working? Thanks for your time.
This is how I force the SOC and my analog init code is below.
// SW force ADC SOC
AdcRegs.ADCSOCFRC1.all = 0x003F; // initiate SOC0 - SOC5
void InitAnalog(void)
{
// power on and enable both ADCs
InitAdc1();
InitAdc2();
// Enalbe the various analog 1 and analog 2 input pins
EALLOW;
GpioG2CtrlRegs.AIOMUX1.bit.AIO2 = 2; // Configure AIO2 for A2 (analog input) operation
GpioG2CtrlRegs.AIOMUX1.bit.AIO4 = 2; // Configure AIO4 for A4 (analog input) operation
GpioG2CtrlRegs.AIOMUX1.bit.AIO6 = 2; // Configure AIO6 for A6 (analog input) operation
GpioG2CtrlRegs.AIOMUX1.bit.AIO12 = 2; // Configure AIO12 for B4 (analog input) operation
GpioG2CtrlRegs.AIOMUX2.bit.AIO18 = 2; // Configure AIO18 for A2 (analog input) operation
GpioG2CtrlRegs.AIOMUX2.bit.AIO20 = 2; // Configure AIO20 for A4 (analog input) operation
GpioG2CtrlRegs.AIOMUX2.bit.AIO22 = 2; // Configure AIO22 for A6 (analog input) operation
GpioG2CtrlRegs.AIOMUX2.bit.AIO28 = 2; // Configure AIO28 for B4 (analog input) operation
//ADC control and interrupt
Adc1Regs.ADCCTL2.bit.ADCNONOVERLAP = 1; // Set ADC to non-overlap mode
Adc1Regs.SOCPRICTL.bit.SOCPRIORITY = 4; // SOC0-SOC3 are high priority
Adc1Regs.ADCCTL1.bit.INTPULSEPOS = 1; // EOC trips after conversion result is latched
Adc1Regs.INTSEL1N2.bit.INT1E = 1; // Enable ADCINT1
Adc1Regs.INTSEL1N2.bit.INT1CONT = 0; // Disable ADCINT1 Continuous mode (must clear ADCINT1 flag before next int can occur)
Adc1Regs.INTSEL1N2.bit.INT1SEL = 5; // setup EOC5 to trigger ADCINT1
Adc2Regs.ADCCTL2.bit.ADCNONOVERLAP = 1; // Set ADC to non-overlap mode
Adc2Regs.SOCPRICTL.bit.SOCPRIORITY = 6; // SOC0-SOC5 are high priority
//Adc2Regs.ADCCTL1.bit.INTPULSEPOS = 1; // EOC trips after conversion result is latched
//Adc2Regs.INTSEL1N2.bit.INT1E = 1; // Enabled ADCINT1
//Adc2Regs.INTSEL1N2.bit.INT1CONT = 0; // Disable ADCINT1 Continuous mode (must clear ADCINT1 flag before next int can occur)
//Adc2Regs.INTSEL1N2.bit.INT1SEL = 3; // setup EOC3 to trigger ADCINT1
// Select the source for triggers
AnalogSysctrlRegs.TRIG5SEL.bit.TRIG5SEL = 0; //disable trigger 5, going to SW force SOC
// setting these to 0 will allow the adc to go through inputs sequentially (not using both sample & holds at same time)
// setting these to 1 will allow the adc to go through inputs simultaneously
AdcRegs.ADCSAMPLEMODE.bit.SIMULEN0 = 0;
AdcRegs.ADCSAMPLEMODE.bit.SIMULEN2 = 0;
AdcRegs.ADCSAMPLEMODE.bit.SIMULEN4 = 0;
AdcRegs.ADCSAMPLEMODE.bit.SIMULEN6 = 0;
AdcRegs.ADCSAMPLEMODE.bit.SIMULEN8 = 0;
AdcRegs.ADCSAMPLEMODE.bit.SIMULEN10 = 0;
AdcRegs.ADCSAMPLEMODE.bit.SIMULEN12 = 0;
AdcRegs.ADCSAMPLEMODE.bit.SIMULEN14 = 0;
// set the channels for each adc
// note: the conversion results will be placed into the SOC# result register.
Adc1Regs.ADCSOC0CTL.bit.CHSEL = 0x06; // ADC1-A6
Adc1Regs.ADCSOC1CTL.bit.CHSEL = 0x06; // ADC1-A6
Adc1Regs.ADCSOC2CTL.bit.CHSEL = 0x06; // ADC1-A6
Adc1Regs.ADCSOC3CTL.bit.CHSEL = 0x00; // ADC1-A0
Adc1Regs.ADCSOC4CTL.bit.CHSEL = 0x03; // ADC1-A3
Adc1Regs.ADCSOC5CTL.bit.CHSEL = 0x0F; // ADC1-B7
Adc2Regs.ADCSOC0CTL.bit.CHSEL = 0x02; // ADC2-A2
Adc2Regs.ADCSOC1CTL.bit.CHSEL = 0x02; // ADC2-A2
Adc2Regs.ADCSOC2CTL.bit.CHSEL = 0x02; // ADC2-A2
Adc2Regs.ADCSOC3CTL.bit.CHSEL = 0x0F; // ADC2-B7
// set the acquisition time for the sample & hold window.
Adc1Regs.ADCSOC0CTL.bit.ACQPS = 0x06; // sample window is 7 cycles long (minimum value is 0x06 - 7 cycles)
Adc1Regs.ADCSOC1CTL.bit.ACQPS = 0x06; // sample window is 7 cycles long (minimum value is 0x06 - 7 cycles)
Adc1Regs.ADCSOC2CTL.bit.ACQPS = 0x06; // sample window is 7 cycles long (minimum value is 0x06 - 7 cycles)
Adc1Regs.ADCSOC3CTL.bit.ACQPS = 0x06; // sample window is 7 cycles long (minimum value is 0x06 - 7 cycles)
Adc1Regs.ADCSOC4CTL.bit.ACQPS = 0x06; // sample window is 7 cycles long (minimum value is 0x06 - 7 cycles)
Adc1Regs.ADCSOC5CTL.bit.ACQPS = 0x06; // sample window is 7 cycles long (minimum value is 0x06 - 7 cycles)
Adc2Regs.ADCSOC0CTL.bit.ACQPS = 0x06; // sample window is 7 cycles long (minimum value is 0x06 - 7 cycles)
Adc2Regs.ADCSOC1CTL.bit.ACQPS = 0x06; // sample window is 7 cycles long (minimum value is 0x06 - 7 cycles)
Adc2Regs.ADCSOC2CTL.bit.ACQPS = 0x06; // sample window is 7 cycles long (minimum value is 0x06 - 7 cycles)
Adc2Regs.ADCSOC3CTL.bit.ACQPS = 0x06; // sample window is 7 cycles long (minimum value is 0x06 - 7 cycles)
EDIS;
} // end of InitAnalog
