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Some questions about HVPSFB-PCMC's HVPSFB-DPL-ISR.asm

user4559636
Prodigy 80 points
Other Parts Discussed in Thread: TMS320F28035

Hi,

I have some questions about HVPSFB-PCMC's HVPSFB-DPL-ISR.asm(TMS320F28035). These problems have troubled me for a lot of days.

1) The interrupt setting is "EPwm1Regs.ETSEL.bit.INTSEL = ET_CTRU_CMPA". So I think the interrupt frequency is 100KHz, but the user's guide(TIDU248) say "a run-time section which executes at twice the PWM". How? Where is  it setting?

2) To implement the SR's dead band because of "EPwm4Regs.DCFWINDOW" or those NOPs?

3) Dmax=0.734375 and the HVPSFB-DPL-ISR.asm is around 165 cycles max, could these two things be related?

Thanks!

  • 0
    TI__Genius 10820 points

    Hi,

    1) The interrupt setting is "EPwm1Regs.ETSEL.bit.INTSEL = ET_CTRU_CMPA". So I think the interrupt frequency is 100KHz, but the user's guide(TIDU248) say "a run-time section which executes at twice the PWM". How? Where is  it setting?

     - The interrupt trigger configuration is changed by the ISR every time it is executed such that the ISR is triggered once every half PWM switching cycle.

    2) To implement the SR's dead band because of "EPwm4Regs.DCFWINDOW" or those NOPs?

     - The DCFWINDOW along with compare registers are used to generate correct waveforms for SR switches. In this configuration there is no need for a dead-band between the SR switches.

    3) Dmax=0.734375 and the HVPSFB-DPL-ISR.asm is around 165 cycles max, could these two things be related?

     - These two are not related. Dmax provides a max clamp for the controller (2P2Z) output.

    I hope this helps.

    Hrishi

  • 0 in reply to Hrishi Nene
    Prodigy 80 points

    Thank you very much.

    Can you tell me which sentence changes the interrupt trigger configuration? And the NOP, what is its purpose? 

     

  • 0 in reply to Hrishi Nene
    Prodigy 80 points
    And I have another question to ask you for help:
    the configuration is:
    (*ePWM[n+3]).CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on CTR = Zero:TBCTR = Ox0000
    (*ePWM[n+3]).CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Shadow mode
    (*ePWM[n+3]).CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
    (*ePWM[n+3]).CMPCTL.bit.SHDWBMODE = CC_SHADOW;

    so the CMPA and CMPB registers are shadow register.
    And:
    MOV @_EPwm4Regs.AQCTLB, #0x0201
    MOV @_EPwm4Regs.AQCTLA, #0x0002
    NOP
    NOP
    NOP
    NOP
    NOP
    NOP
    NOP
    NOP
    NOP
    NOP
    NOP
    NOP
    NOP
    NOP

    NOP
    NOP
    NOP
    NOP

    ; MOVW DP,#(AQCTLA4>>6)
    MOV @_EPwm4Regs.AQCTLB, #0x0200


    I have a doubt: EPwm4Regs.AQCTLB is set twice, why?
  • 0 in reply to user4559636
    Prodigy 80 points
    The AQCTLA/B is not a shadow register. Does this mean just CMPA and CMPB come from last half cycle?
  • 0 in reply to user4559636
    Prodigy 80 points

    I get it.

    MOV  @_EPwm1Regs.ETSEL, #0x0B0D

    MOV  @_EPwm1Regs.ETSEL, #0x0B0C

    Thanks!

  • 0 in reply to user4559636
    TI__Genius 10820 points

    Hi,

    The NOPs between the AQCTL changes make sure that the counter zero or period event occurs between these AQCTL changes (during the NOPs). On newer devices (F2837x, F2807x, and newer) this is not required.

    Hrishi

  • 0 in reply to Hrishi Nene
    Prodigy 30 points

    Hrishi Nene said:
    The NOPs between the AQCTL changes make sure that the counter zero or period event occurs between these AQCTL changes (during the NOPs). On newer devices (F2837x, F2807x, and newer) this is not required.

    Hrishi,

    Does it mean I can simply remove these 18-20 NOP's out of the assembly code in the ISR if I run it, let's say, on Delfino MCU?

    Is it now supported by the hardware of newer MCU's?

    Thank you.

  • 0 in reply to Aleksandr Sorokin
    TI__Genius 10820 points

    Aleksandr,

    No, simply taking out the NOPs won't do it. On the new devices there are new configuration registers/bits that have been added in the action qualifier, dead-band and trip-zone sub-modules. These registers need to be configured correctly to get this to work right.

    We hope to release some examples for doing this soon.

    Hrishi