This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Inconsistent definitions in DSP2803x_EPwm_defines.h

Other Parts Discussed in Thread: CONTROLSUITE

Hi

In DSP2803x_EPwm_defines.h (can be found at //controlSUITE/device_support/f2803x/v130/DSP2803x_common/include)

the definitions of DBA_ENABLE and DBB_ENABLE are different to the other files, e.g: DSP2802x_EPwm_defines.h,

DSP2806x_EPwm_defines.h and DSP2833x_EPwm_defines.h.

Ti should keep all these definitions consistent.

thanks,

Jiakai

  • Hi Jiakai,

    The DBA_ENABLE and DBB_ENABLE definitions should be consistent across the devices you mentioned.
    That being said, these files will vary among devices because the peripheral design changes across devices. Table 34 of the C2000 Real-Time Control Peripherals Reference Guide found at www.ti.com/lit/ug/spru566l/spru566l.pdf list the changes made to the ePWM peripheral and the devices affected by the changes.

    Elizabeth

  • Hi Elizabeth,

    I have checked ePWM documents, all of F2802x, F2803x and F2806x uses type 1 ePWM.
    Even for F2833x, it uses type 0 ePWM, but there is no difference in dead band registers
    between type 0 and type 1 ePWM.

    I wrote a F2833x program to use ePWM to control half-H bridge converters by referring
    to 3.5 in SPRUG04A.
    In the program I use dead band to avoid short circuit. DBCTL registers are set as follows:
    EPwm1Regs.DBCTL.bit.OUT_MODE = DBB_ENABLE;
    EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HI;
    EPwm1Regs.DBCTL.bit.IN_MODE = DBA_RED_DBB_FED;

    Then I migrate this program to F2802x, F2803x and F2806x. PWM action is same in F2802x and F2806x,
    only F2803x program has different PWM action. After checking PWM definitions I found DBB_ENABLE value
    is 1 in F2803x, 2 in other CPUs.

    By the way, I don't think my dead band setting for half-H bridge PWM control is good enough, do you have any good
    idea to set dead band registers for half-H bridge PWM control?

    thank you very much.
    Jiakai
  • Hi Jiakai,

    Yes, those definitions should’ve been the same across those files, and this will be correct in a future controlSUITE release. Thank you for bringing this to our attention.

    Regarding your question about the dead-band module, my suggestion is to review how you configured the DBRED and DBFED registers. These registers specify the amount of delay for rising edge and falling edge, respectively. In your configuration, the value of DBRED register shouldn't matter as rising-edge delay is disabled by setting OUT_MODE to DBB_ENABLE (01). It is important that the dead-time is smaller than the minimum generated pulse. Otherwise, the dead-band can turn off outputs smaller than the dead-time.

    Elizabeth

  • Hi Jiakai,

    I’m checking with you to see if this issue has been resolved.

    Also, a further clarification on the DBCTL OUT_MODE bit. When the bit is set to 0x1 (DBBENABLE) – the falling-edge delay is on output EPWMxB, and the rising-edge delay is disabled. When the bit is set to 0x2 (DBAENABLE) , the rising-edge delayed signal is on output EPWMxA, and the falling-edge delay is disabled. These values are currently swapped in the DSP2833x_EPwm_Defines.h file, so I’m filing a report to correct this.

    Elizabeth
  • Hi Elizabeth,

    This issue has been solved. Thank you very much.

    I don't know if I need to open a new thread. The question is when I use F2803x ePwm

    to implement a Half-H Bridgr converter (see 3.5 Controlling Multiple Half-H Bridge Converters

    in SPRUGE9E), what's the normal way to add dead time?

    Thanks,

    Jiakai

  • Hi Jiakai,

    The common configuration of the dead band is to set EPWMxA as the source for both falling-edge and rising-edge delays by setting IN_MODE to 0 and to enable both rising edge and falling edge delays by setting OUT_MODE to 3. Table 14 Classical Dead-Band Operating Modes shows the other typical dead band configurations.

    Elizabeth
  • Hi Elizabeth,

    I don't know if you are considering EPWMxB is a complementary output of EPWMxA.

    My sitution is different, please check the following picture, I need to add dead time in 2 areas marked 

    by red boxes.

    thanks,

    Jiakai

  • Hi Jiakai,

    The POLSEL bits of DBCTL register determine whether the outputs will be inverted. Setting POLSEL to 0 is active high mode, and neither EPWMxA nor EPWMxB outputs are inverted. This is how the code you shared above set POLSEL, so I believe you have the correct setting. Setting POLSEL to 2 is how to invert EPWMxB.

    Elizabeth
  • thanks, I'll test it to check which combination is best for my situation.

    Jiakai