1. On section 6.3.1 of SPRS880F document, the uPP MSG RAM memory map is shown below.
On section 24.4.9 of SPRUHM8E document, the uPP MSG RAM memory map is shown below.
The start address and end address of uPP MSG RAM confuse me a lot. Which address should be used from the view of the user program?
2. On section 24.4.2.1 of SPRUHM8E document, it mentioned that “Window Address (CHxDESC0.ADDR) - The location in uPP data memory of the first byte in the data buffer”. Is this uPP data memory corresponding to the uPP MSG RAM? What’s the meaning of the data buffer?
3. There are many terms of memory named as “uPP FIFO”, “Channel buffer”, “uPP MSG RAM”. But the figure shown below does not explicitly describe the data flow between these memories.
4. On section 24.3.3 of SPRUHM8E document, it mentioned that “A module clock that controls its internal logic and CPU interface. This is driven by CPU1.SYSCLK”. Does this module clock refer to CPU1.SYSCLK or PER2.SYSCLK?
5. Is there any sample code for uPP of TMS320F28377D?