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uPP of TMS320F28377D

Other Parts Discussed in Thread: TMS320F28377D, CONTROLSUITE

1. On section 6.3.1 of SPRS880F document, the uPP MSG RAM memory map is shown below.

On section 24.4.9 of SPRUHM8E document, the uPP MSG RAM memory map is shown below.

The start address and end address of uPP MSG RAM confuse me a lot. Which address should be used from the view of the user program?

2. On section 24.4.2.1 of SPRUHM8E document, it mentioned that “Window Address (CHxDESC0.ADDR) - The location in uPP data memory of the first byte in the data buffer”. Is this uPP data memory corresponding to the uPP MSG RAM? What’s the meaning of the data buffer?

3. There are many terms of memory named as “uPP FIFO”, “Channel buffer”, “uPP MSG RAM”. But the figure shown below does not explicitly describe the data flow between these memories. 

4. On section 24.3.3 of SPRUHM8E document, it mentioned that “A module clock that controls its internal logic and CPU interface. This is driven by CPU1.SYSCLK”. Does this module clock refer to CPU1.SYSCLK or PER2.SYSCLK?

5. Is there any sample code for uPP of TMS320F28377D?

  • Hi,

    controlSUITE has example code (upp_sdr_tx and upp_sdr_rx). These examples should be able to answer most of the questions related to MSGRAM address and data flow.

    On below -

    4. On section 24.3.3 of SPRUHM8E document, it mentioned that “A module clock that controls its internal logic and CPU interface. This is driven by CPU1.SYSCLK”. Does this module clock refer to CPU1.SYSCLK or PER2.SYSCLK?

    PERx.SYSCLK and CPUx.SYSCLK is almost same. CPUx.SYSCLK is gated with peripheral clock enable for each IP and this gated clock is called PERx.SYSCLK.

    Regards,

    Vivek Singh

  • Does the following EMIFx clock refer to PERx.SYSCLK? If yes, then the CPUx.SYSCLK is not the same as PERx.SYSCLK.

  • Hi,

    I have read the example code in controlSUITE. Another question is the difference between register INTENSET and INTENCLR. Are the following codes equivalent to each other?

    code 1: UppRegs.INTENCLR.all = uPP_INT_EOLI; /* write 1 to clear interrupt*/

    code 2: UppRegs.INTENSET.all &= ~uPP_INT_EOLI; /* write 0 to disable interrupt*/

  • Hi,

    Table clearly mention what clock is connect for EMIF. EMIF also has the clock gating but in addition has clock divider which divides the source clock so not same the case.

    Regards,

    Vivek Singh
  • Hi,

    I have read the example code in controlSUITE. Another question is the difference between register INTENSET and INTENCLR. Are the following codes equivalent to each other?

    code 1: UppRegs.INTENCLR.all = uPP_INT_EOLI; /* write 1 to clear interrupt*/

    code 2: UppRegs.INTENSET.all &= ~uPP_INT_EOLI; /* write 0 to disable interrupt*/

    No, both are not same. Writing '0' in INTENSET register does not disable the interrupt. Writing '0' has no impact in this register. It's only for setting the bit to '1' and for clear one need to use the CLR register and write '1' there. Look like we need to add this note in the document to avoid the confusion. We'll as this in next document update.

    Regards,

    Vivek Singh 

  • Sorry, I misread the PERCLKDIVSEL register.