Hello,
I want to read the MRESC register on startup to determine and report the reason for the reboot of the code. I'm looking for a level of granularity that distinguishes between a normal power on reset, an ARM watchdog timeout and every thing else. The MRESC register is certainly up to the task. My question is in regards to the the behavior of MRESC when the code is being run with the debugger. Breakpointing seems to reveal that the MRESC register is cleared to 0, even though there has been a power on reset at some point in the life of the Concerto prior to the current debug session.
Seems like connecting debugger to the target, powering on the target, and launching CCS should leave the XRSn and/ or POR bits set to 1.
Nothing I can see in my GEL files are clearing MRESC.
Can you comment please? Thank you.
Best regards,
Steve C.
