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F2837xD: ADC minimum sampling window spec

David M. Alter
Guru 61235 points

C2000 Team,

The F2837xD datasheet, SPRS880G, Table 5-43 shows two specs for minimum ADC sampling window: 320 ns, and 1 ADCCLK.

In light of the first row in the table, the minimum ADCCLK is 5 MHz, which is 200 ns.  Therefore, you cannot achieve 1 ADCCLK for the minimum sampling window since that would violate the 320 ns spec.  It seems in reality the minimum sampling window is 2 ADCCLK in 16-bit mode.

There is somewhat misleading information as well in Table 10-29 of the TRM, SPRUHM8E, which states that the minimum acquisition time is one ADCCLK cycle, with no mention of the 320 ns (16-bit mode) minimum.

Can you advise?

- David

  • 0
    TI__Guru 60865 points

    Hi David,

    You need to meet both requirements.

    If you use a S+H window less than 320ns (low impedance input) or less than whatever is predicted by using the ADC input model for 1/4 LSB settling (higher impedance inputs) then you can get input settling issues leading to signal attenuation and/or "memory cross-talk" (some residual voltage left from the previous conversion influencing the current conversion).

    If you configure a S+H window such that the time is less than 1 ADCCLK, then the ADC conversion timings won't work correctly and you will get garbage results.

    Normally the only one you need to worry about is the 320ns or whatever is predicted by the input model.  However, if your are running the SYSCLK really slow then there could be an ACQPS value that gives enough time for adequate input settling, but that produces invalid timings.  I think as you point out, due to ADCCLK being limited to 5MHz on the slow side, this situation will only be possible in 12-bit mode. 

    We'll edit the documentation to make things more clear.