Hello,
My TMS320F28335 CCS code is generating three PWM signals: PWM1a, PWM1b, and PWM2a. Trying to keep things simple for the sake of this question, the objective is for PWM2a to capture the falling edge of PWM1a so as PWM1a is falling, PWM2a should rise at the exact same time. I have the compare value to be the same for I'm more wondering if the synchronization is wrong. I have attached the PWM1 compare values part of the code with a dead band. I have also attached the initialization codes for both PWM1 and PWM2. Any ideas on what could be the problem?
void InitEPwm1Example()
{
EPwm1Regs.TBPRD = EPWM_TIMER_TBPRD; // Set timer period // CW: Intial switching period is 12000*2/150000000=0.00016s (6.25kHz)
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
// Setup counter mode
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up down
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading //Was TB_ENABLE
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;//TB_SYNC_IN; // Sync down-stream module
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// Setup shadowing
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Modify the comparison
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on event A, up count
EPwm1Regs.AQCTLA.bit.CAD = AQ_SET; // Clear PWM1A on event A, down count
EPwm1Regs.AQCTLB.bit.CBU = AQ_SET; // Clear PWM1B on event B, up count
EPwm1Regs.AQCTLB.bit.CBD = AQ_CLEAR; // Set PWM1B on event B, down count
EPwm1Regs.ETSEL.bit.SOCAEN = 1;
EPwm1Regs.ETSEL.bit.SOCASEL =ET_CTR_PRD; // ET_CTR_PRD;
EPwm1Regs.ETPS.bit.SOCAPRD = ET_1ST;
epwm1_info.EPwmTimerIntCount = 0; // Zero the interrupt counter
epwm1_info.EPwmRegHandle = &EPwm1Regs; // Set the pointer to the ePWM module
EALLOW;
EPwm1Regs.HRCNFG.all = 0x0;
EPwm1Regs.HRCNFG.bit.EDGMODE = HR_BEP; //HR_FEP; // MEP control on falling edge
EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP;
EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO;
EDIS;
}
void InitEPwm2Example()
{
// Setup TBCLK
EPwm2Regs.TBPRD = EPWM_TIMER_TBPRD; // Set timer period
EPwm2Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter
// Setup counter mode
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Enable phase loading
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// Setup shadowing
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Modify the comparison
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up count
EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM1A on event A, down count
EPwm2Regs.AQCTLB.bit.ZRO = AQ_CLEAR; // Clear PWM1B on event B, up count
EPwm2Regs.AQCTLB.bit.CBD = AQ_CLEAR; // Set PWM1B on event B, down count
epwm2_info.EPwmTimerIntCount = 0; // Zero the interrupt counter
epwm2_info.EPwmRegHandle = &EPwm2Regs; // Set the pointer to the ePWM module
EALLOW;
EPwm2Regs.HRCNFG.all = 0x0;
EPwm2Regs.HRCNFG.bit.EDGMODE = HR_BEP; // // MEP control on rising edge!!!!!!!!!!!!!!
EPwm2Regs.HRCNFG.bit.CTLMODE = HR_CMP;
EPwm2Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO;
EDIS;
}
//Here is the PWM1 compare values with dead band
EPwm1Regs.CMPA.half.CMPA = CMP_a; // Set compare A value
EPwm1Regs.CMPB = CMP_a; // Set Compare B value
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm1Regs.DBFED = DEAD_TIME;
EPwm1Regs.DBRED = DEAD_TIME;