Dear Community,
1) I'm wondering how the MEP-STEP logic is able to achieving fine time steps of around 150ps. The reference manuals
do only talk about the results but do not explain the system behind it. The data manuel informed me about multiple delay lines in one system but
i would like to know further details. The CPU of the F28377S does support the limit of 200MHz but the MEP STEPS require a much higher clock frequency.
2)I´m able to see the mechanism behind HR-Duty control but i´m wondering how the HRPeriod works, because if i want to extend my last TBPeriod step with MEP-Steps to achieve my exact Frequency, the new TBCLK should start, for an exact frequency, after the MEPSTEPs. But the problem is that the TBCLK is fed from the Systemclock and should not be able to be hold back till the hrperiod MEP-steps are finished (and continue couting as if no MEP-steps exist). So basicly the Period should always stay the same and only the Duty Cycle should be changed by extending the last TBPeriod count.
I hope i could describe my questions good enough and that i find help here.
Thank you!
