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C28x SCI Idle Line Mode Speed

Other Parts Discussed in Thread: AM3359

Hello,

In the SCI peripheral of the C28x series processors there are two modes of operation: Idle Line Mode and Address Bit Mode.

The manual states that in the Idle Line Mode there is an idle time of less than 10 bits between every byte + control data that you send.

This can give you more than 100% overhead for every 8 bits that you send !

We want to work at the high speeds of 7-8 mbps which is theoretically achievable according to the manual.

The question is what will be the idle time between every data byte that we send and how this will limit our throughput.

What is the real penalty in the Idle Line Mode ? How much is this less than 10 bits idle time ? Can this be stated exactly ?

Thanks to all !

  • Hello George,

    Idle line and Address bit modes are there for multi-drop communication.  So first, if you are just looking for a regular UART with point-to-point connection, you don't need them.  What you would do there is configure for Address bit mode, and NOT set the ADDR bit in the SCI control register.  This makes the SCI act like a regular UART.[CORRECTION 8/30/16, D. Alter:  For regular UART, use IDLE LINE mode and do not set SLEEP=1 for the slave nodes].

    The multi-drop modes are used to differentiate between an address frame and an data frame in a multi-drop environment.  Basically, the master node has to first send out a byte that indicates who he is talking to.  The slaves SCIs are all in an sleep state (SLEEP bit was set).  When they receive an address frame, they wake up and receive the byte (the address).  The SCIs then interrupt their CPUs.  The CPUs can look at the address, and decide if the message is for them or not.  If not for them, they put the SCI back to sleep so they don't get anymore interrupts until the next address frame.  If the message is for them, they leave things alone and let the SCI receive the data frames.

    So, the idea behind idle mode is that you leave at least 10 idle bits after the last transmission to indicate an address frame.  This is how the sleeping SCIs wake up.  If they see 10 or more idle bits, they wake up on the next reception.  So, you are only leaving the idle bits before an address frame.  The assumption is that you have more than a single byte of data that you transmit in each "Packet".  That is, send an address, followed by multiple bytes of data.

    If you have less than 9 bytes of data in a packet, then ADDRESS bit mode is more efficient since it has only 1 bit of overhead for each byte sent (including the address bit).  At 9 bytes of data, IDLE LINE and ADDRESS bit modes are break-even.  More than 9 bytes of data in a packet and IDLE LINE mode is more efficient.

    Regards,

    David

  • Thanks for the quick reply, David.

    We use Delfino Double Core chip, and we have only one recipient of the data, and it is AM3359 Sitara Processor which has UART within the PRU-ICSS.

    So in our case we should not be dealing with the modes at all as you say.

    And even if we would want to use the Idle mode, if I understood you correctly, between the data bytes there is no idle bits at all, there are only 10 or more idle bits before the address byte to indicate the begining of the transmission. Correct ?
  • David, thank you very much for your support.

    Now, let me ask you the following question:

    Let's assume that I use this UART as the regular UART.
    And now I send the stream of data - start bit, byte of data, parity, and the stop bit. And then the next byte, and the next ...
    After the stop bit and the next start bit - are there any idle bits ?
    In other words - I can send the data really in sequential way ? Without any penalty ? One byte after the other, only with start and stop bits, without any idle bits in between ?

    Regards, George.
  • George,

    In IDLE LINE mode, the idle bits are only sent if the user wants them to.  That is, either deliberately wait at least 10 bits before sending an ADDRESS frame, or you can set the TXWAKE bit in the SCI and this will cause the SCI to send 11 idle bits (you can read about this in the TRM).  So, for a regular UART, just don't send idle bits, and don't put the receivers (slaves) asleep (do not set SLEEP=1).

    If you are running as a regular UART, you will have no time space between data values if you keep the transmitter buffer loaded.  If you let the buffer run down, then you will stop transmitting and get idle time.  this is normal stuff though.

    - David

  • sir , I have doubt about idle line mode . If we select idle line mode and have following configuration TXWAKE=0; and SLEEP=0;
    then is it possible to receive regular UART (8-N-1) signal on device configured to idle line mode with above configuration.
  • Is there any need to configure SCI differently to receive regular UART signal, other than TXWAKE=0; and SLEEP=0;
    Thanks.
  • You do not need to configure anything else differently to operate in regular UART mode.

    - David