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TMS320F2837xD - EMIF to both Async Memory & SDRAM

SSF
Intellectual 2025 points

Hi Team,

Looking at figure 25-15 on p. 2447 of the TRM for the TMS320F2837xD, I have the following question:

On the FLASH memory the Address bus uses the Delfino’s Addr[12:1] and then they show Addr[18:13] driven by GPIOs on the TI DSP.
Since the DQM0 to DQM3 (byte enables) are multiplexed with the EM1_Addr[15:18], my question is can I still use the EM1_Addr[15:18] as address bits of the FLASH or do I have to specifically use GPIOs on the Delfino to the Flash memory to cover Addr[15:18]?

Thanks,
Steve

  • 0
    TI__Guru** 109105 points

    Hi Steve,

    You should be able to use the address pins muxed with DQM as address pins but please note that A13 and A14 are muxed with CAS/RAS lines so these should not be used. Due to this you'll have discontinuity in address space.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    TI__Expert 6090 points
    Hi Vivek,

    I thought the interface was specifically designed to accommodate both SDRAM and Asynch mode.

    Now I hear that the fact that CAS and RAS are muxed with address lines means they ‘should not’ be used for Asynch address lines?
    Please note, the difficulties resulting from the “discontinuity in address space” can get extremely messy, hence my concern.

    Is this advice given because the signals can not be muxed real-time while the other signals (such as the DQM that were discussed) are muxed real-time?
    Would the process of changing the functionality of the pins have to be performed each time as a separate action by software, as would the utilization of other GPIO for the function of serving as those address pins?

    With the CS line to the SDRAM inactive during Asynch mode, the RAS and CAS signals will not have any effect on the SDRAM. So it makes it hard to understand the risk associated with using these multipurpose muxed pins.

    You say ‘should not’ as though it can work but it is seen as risky or difficult. Can you please explain the risk or difficulty?

    Appreciate your insight!
    Thank you,
    Brad
  • 0 in reply to Go Bravos
    TI__Guru** 109105 points

    Hi Brad,

    This recommendation is more on the same thought what you mentioned in last point. RAS/CAS are critical control signal for SDRAM hence we don't recommend to connect these lines to any other logic on board. In general these signals are not meant to be connected to multiple devices. As you correctly mentioned, if chip select is inactive then it should not matter and may work fine but it's not guaranteed to work in all the conditions hence user need to make sure it works in all the conditions, if they are using it.

    We understand the issue w.r.t. discontinuity because of this hence we suggest using GPIO pins for higher address lines for ASYNC. On our next device we are going to provide additional mux options for higher address lines to avoid this.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    TI__Expert 6090 points
    Hi Vivek,
    Thank you very much. I have a few follow-up questions.

    When you say “it's not guaranteed to work in all the conditions” is that because you haven't tested the Delfino using both an SDRAM and an Asynch memory device on the EMIF bus?

    Is there a specific flaw in the EMIF bus design that creates the opportunity for it to not work properly?

    I would avoid using the signals for anything other than RAS and CAS, because while it is not DDR, it is pretty tight timing on the bus. However the performance problems resulting from a ‘gap’ or from requiring software to each time manually drive the address bits are unacceptable that I have to try and make it work.

    You mention a “next device” with “additional mux options for higher address lines”. Is there going to be a “next device” in the Delfino family? If yes, when?

    Best regards,
    Brad
  • 0 in reply to Go Bravos
    TI__Guru** 109105 points

    Hi Brad,

    When you say “it's not guaranteed to work in all the conditions” is that because you haven't tested the Delfino using both an SDRAM and an Asynch memory device on the EMIF bus? 

    It's been tested but without connecting RAS/CAS signals to address lines of ASYNC device.

    Is there a specific flaw in the EMIF bus design that creates the opportunity for it to not work properly?

    No known design issue. It's more of a timing concern.

    I would avoid using the signals for anything other than RAS and CAS, because while it is not DDR, it is pretty tight timing on the bus. However the performance problems resulting from a ‘gap’ or from requiring software to each time manually drive the address bits are unacceptable that I have to try and make it work.

    Understand the concern. This mode is generally used for connecting FPGA on ASYNC interface and SDRAM memory on SDRAM interface. If you are planning to use the ASRAM memory on ASYNC interface then it could be an issue if assesses are not linear.

    You mention a “next device” with “additional mux options for higher address lines”. Is there going to be a “next device” in the Delfino family? If yes, when?

    Device type is not decided yet but a device with EMIF will have this issue addressed. We do not have timeline yet for this.

    Regards,

    Vivek Singh