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How to improve power ratting and power factor Based on 700w ILPFC kit

Yuqin
Prodigy 155 points
Other Parts Discussed in Thread: SFRA

Hello,

I am a Chinese student ,with a long time learned about the 2 phases Interleaved PFC kit, I made my 3.5 kw ILPFC hardware based on it.My PFC board is alsodesigned to connect a F28035 control card without a board Emulator through DIMM100. So I made a extra board emulator XDS100V1, which designed only withFT2232D and ISO724xs,  use to connect my control card through 16 pin header(14 pins Jtag and 2 pins SCI) .

With the help of the ILPFC V1.1 code project , my pfc board works well at 110V/50Hz AC input at output power range 100~600w,and the PF is 0.99.Unfortunately,when I go on to add output power,the output voltage is down .The same situation happened when I add output power up to 800W under 230V/50Hz AC input.No more than that , the input current is not sin cave .

Therefor ,I want to adjust the control loop parameters . CCS could programm and run the target well until I change the Input AC voltage from 0 to 120V.I mean that while the Vbus is reaching 160V (PFC open voltage),CCS can't connect target anymore .The test data is upoload.

Now my problem is that

1. is there any one could guide me to improve my board emulator's anti-noise capacity?

2.without the Emulator ,could I adjust loop parameters using Compensator on main.cfg page?

3.To improve output power ratting and maintain the output voltage, which way should I think about?

4.to improve PF like below figure ,the outer Vloop or inner Cloop which one should I adjust?Could anyone tell me how to adjust?

Thank you!

  • 0 in reply to Yuqin
    TI__Genius 10995 points

    spra439d.pdfspru641.pdf

    1. is there any one could guide me to improve my board emulator's anti-noise capacity?

    Please see the attached files. These give guidelines for designing emulator circuits.

    2.without the Emulator ,could I adjust loop parameters using Compensator on main.cfg page?

    No, you cannot. You need to have the Emulator connected. Then design the compensation, recompile & reload the code. Then RUN the code.

    3.To improve output power ratting and maintain the output voltage, which way should I think about?

    Does your current sense circuit (sense resistor and OPAMP gain & filter) allow for higher current sense in your circuit? Does you DC bus capacitor allows for higher power. These are all basic power stage design considerations. This kit does not discuss about PFC power stage design. It discusses how to design the compensation only after a power stage has been designed. If you need help on power stage design there are many application report on TI website on how to design a PFC power stage. Pls review those.

    4.to improve PF like below figure ,the outer Vloop or inner Cloop which one should I adjust?Could anyone tell me how to adjust?

    Resolve the issue #3 first. Then for PFC current loop you have to maintain good loop gain, bandwidth and phase margin in order to get good power factor. For example, your loop gain plot should show at least 30~40dB gain around 100Hz, then rolling off at -20dB/dec, with BW of at least 3~4kHz and PM=45 (at least).

    Also, PFC voltage loop bandwidth has to be around 15Hz only. If it is higher than this (100Hz or more) then your power factor will be bad.

    Hope this helps.

    Shamim

  • 0 in reply to Shamim Choudhury
    Prodigy 155 points

    Hi Shamim,

    Thank you very much! (\(^o^)/YES!

    1. About guide of design emulatot.

    With your help, I reviewed the design of emulator and learned about JTAG's timming requirements.Then I give up using the JTAG pod cable ,that is to say, I plug my xds100V1 emulator board on the PFC base board directly through Header.Even though it doesn't work, when I init the startflag = 0 then write startflag =1 in CCS after Vbus>160 ,which the PFC works good but the connection from target to ccs is lossing. Fortunately, I find that someone meets the same situation as mine.

    So I follow the advice and use a Ferrite core based usb cable.After that , the connection cut off but not cut off mostly.

    2. Then I use SFRA to sweep the loop and plot the Bode graph like the below figure.It differs from the modeled graph .So I cant make sure whether it is correct or not, could you please give me some advice about the reason why they are different especially the about the measurement-graph's not smooth?

    3. There are some doubts on the main.cfg page.As it to see below ,how do the helighted parameters work on the source code?If I adjust them which variable of the source code will be changed?

    4. About the IQ24 variable VbusVcmd ,I learn it has  relationship with the amplitude .Could you please tell me your consideration on using it to Adaptive Current Control? For example,

    if(VbusVcmd > _IQ24(0.22))//Load higher than 20%

    So what is the 100% load ,700W ? If so,how do I change the 100% load ?

    Thanks a lot !

    Regards

  • 0 in reply to Yuqin
    Prodigy 155 points

    Sorry about my question #2, I made a mistake ,which I used the COMP9 (NL control loop parameter COMPV1) to turning the inner current loop.With my strange Plant figure like bellow under condition [ Vin=205Vrms,VbusVcmd = 0.5, Vout=363V ,Iout = 1.9A ] in Build 2.Additional there's  the Input voltage&current .

    In terms of the Plant bode figure, I guess the reason why it rolls off then rolls up at 1.5KHz is that my PFC inductor is about 300uH. Do you agree with it? Because of this I could not find suitable 2p2z coeff to keep BW = 3~4KHz .Should I change the PFC inductor value? Or is there an another way to find coeffs?There is the SFR data(to use it in CompDesigner please change expansion .txt to.csv) ,maybe it will help for the question.

    SFRAData.txt 
    Frequency (Hz),OL Magnitude (dB),OL Phase (Deg),Plant Magnitude (dB),Plant Phase (Deg)
150,24.3443450927734,-84.1112213134766,7.43049621582031,26.1431121826172
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178.275497436523,16.1292266845703,-103.40185546875,-0.750030517578125,-27.1869964599609
188.839050292969,15.0815277099609,-105.323486328125,-1.21536254882813,-25.3554229736328
200.028533935547,13.46923828125,-109.463119506836,1.59638977050781,-157.739120483398
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224.435836791992,13.0921630859375,-108.062561035156,-0.224395751953125,-37.3284606933594
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251.821304321289,13.3064727783203,-100.608581542969,-0.753341674804688,-8.26530456542969
266.742736816406,13.7213134765625,-106.383972167969,-2.48147583007813,-27.0733489990234
282.548309326172,14.2224426269531,-107.458435058594,-1.28852844238281,-25.6246948242188
299.290435791016,13.0049591064453,-109.065338134766,-1.57307434082031,-29.6952667236328
317.024597167969,13.1386871337891,-110.290176391602,-1.90653991699219,-31.9237670898438
335.809600830078,11.8836975097656,-111.896209716797,-3.61598205566406,-28.8489837646484
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376.784790039063,11.7230682373047,-112.718887329102,-1.36790466308594,-34.2816467285156
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