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F28075 ADC conversion time

Hi Champ, 

Please let me confirm the ADC conversion time for F28075.

Pattern#1.

On the below case, please check if the conversion time is correct.

-ADC Clock : 30MHz

-Simultaneous Mode

-Number of ADC ch : 6ch

-ACQPS : 8

-Using the same trigger for SOC

Total conversion time = S/W time(9ADCCLK) + Conversion time (13*2ADCCLK) + S/W time(9-7ADCCLK) + Conversion time (13*2ADCCLK) + S/W time (9-7ADCCLK) + Conversion time (13*2ADCCLK) = 300ns+866.67ns+66.67ns+866.67ns+66.67ns+866.67ns = 3033.33ns

 

Pettern#2

In the below case, please check if the conversion time is correct.

And, Is both Sequential Mode and Simultaneous Mode used at the same time? 

For example, ADCINA1, ADCINA3/ADCINAB3 pair, ADCINA7/ADCINB7 pair.

-ADC Clock : 30MHz

-ACQPS : 8

-ADCINA1、ADCINA3/ADCINB3 pair、ADCINA7/ADCINB7 pair

-Using the same trigger for SOC

Total conversion time = S/W time (9ADCCLK) + Conversion time (13*1ADCCLK) + S/W time (9-7ADCCLK) + Conversion time (13*2ADCCLK) + S/W time (9-7ADCCLK) + Conversion time (13*2ADCCLK) = 300ns+433.33ns+66.67ns+866.67ns+66.67ns+866.67ns = 2600ns

Regards,

Furuya

 

  • Hi Kengo,

    The F2807x family of devices doesn't have a simultaneous sampling mode.  Instead, parallel ADCs allow for samples to be converted in parallel.  To determine the timings for a single ADC, see this table in the datasheet:

    There is also a corresponding timing diagram to help interpret the table.

    Note that all cycle counts in the first 4 columns of timings are in SYSCLK cycles (not ADCCLK cycles).  For this device family, all timings always end up being a whole number of SYSCLK cycles.  

    To get simultaneous sampling, just configure 2 ADCs with identical configurations (minus the channel select) and let them convert in parallel.  It is important in this case to ensure that the timings for both ADCs are identical so that they run completely synchronously (we have a section in the TRM that explains this in further detail called "Ensuring Synchronous Operation").  

    Because there are parallel ADCs which can be configured independently, you are no longer required to sample channel pairs like A7/B7 or A1/B1.  Instead, it is perfectly ok to configure ADC-A to sample A1 while ADC-B samples B5 (you just have to use the same ACQPS setting to ensure synchronous operation).

    If you have any further questions about interpreting the timing table or achieving simultaneous sampling feel free to let me know.  

      

  • Hi Devin,

    Thank you for your response.

    In case of F28035, is above conversion time correct?
    It is based on the below reference guide.
    www.ti.com/.../spruge5f.pdf

    Regards,
    Furuya
  • Hi Kengo,

    Yes, your timing calculations appear to be correct for F28035 (and the cycle counts would be the same on similar devices like '02x, '06x, and '05x).

    Yes, you can indeed use a mix of sequential and simultaneous conversions for this device.

    Note that if you enable non-overlap mode, you would lose the "-7" part of "9-7ADCCLK" in the S+H window cycle calculation. Not sure if you have this enabled or not.