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TMS320F28379D: TMS320F28379D

Part Number: TMS320F28379D

I have a problem uploading the code. The error says..

C28xx_CPU1: If erase/program (E/P) operation is being done on one core, the other core should not execute from shared-RAM (SR) as they are used for the E/P code.  Also, CPU1 will be halted to determine SR ownership for the CPU which will run the Flash Plugin code, after which CPU1 will be set to run its application. User code execution from SR could commence after both flash banks are programmed.

I have learnt that it is due to CPU not being halted while uploading.

Can you guide me as to how to halt the CPUs for uploading. Can you also provide a link or document that has more information regarding this.

  • Hi Shiva,

    Did you get above as an error message? Can you provide a snapshot?

    What you copied above from CCS console window is not an error and instead it is a note displayed for the users (when debugger connects to the target) to educate that Flash Plugin code gets executed from shared RAM and hence, applications should consider this fact to make sure that they don't execute from shared RAM on one core while other core is doing it's Flash operations using Flash Plugin. Best would be to load the code to both Flash banks first (when the application has both CPU1 and CPU2 coff files) before executing from both banks.

    Also, note that you should have a fully embedded Flash application (use flash based linker command files) to use Flash Plugin.

    Remember to connect CPU1 as well when using Flash Plugin for CPU2 - This allows Plugin to halt CPU1 for determining/assigning the shared RAM ownership to CPU2.

    Thanks and regards,
    Vamsi
  • Shiva,

    Did you confirm that this is not an error and is just a console window info message? Can I close this thread?

    Thanks and regards,
    Vamsi
  • It was just a console info message

    Thanks for the info
  • Shiva,

    Thank you for the confirmation.  I am closing this thread now.

    Thanks and regards,

    Vamsi