Other Parts Discussed in Thread: CONTROLSUITE
Tool/software: Code Composer Studio
for reference code
#include "DSP28x_Project.h" // Device Headerfile
// Prototype statements for functions found within this file.
void InitEPwm4n5(void);
void InitEPwm2(void);
void InitEPwm3(void);
__interrupt void epwm2_isr(void);
__interrupt void epwm3_isr(void);
__interrupt void adc_isr(void);
void Adc_Config(void);
typedef struct
{
volatile struct EPWM_REGS *EPwmRegHandle4;
volatile struct EPWM_REGS *EPwmRegHandle5;
volatile struct EPWM_REGS *EPwmRegHandle2;
volatile struct EPWM_REGS *EPwmRegHandle3;
Uint16 TBPRD;
Uint16 Duty_Set;
Uint16 MAX_CMP;
Uint16 MIN_CMP;
Uint16 DB_Set;
Uint16 Delay_Set;
Uint16 EPwmTimerIntCountP;
Uint16 EPwmTimerIntCountC;
}EPWM_INFO;
void add_Miss_Pulse_P(EPWM_INFO*);
void add_Miss_Pulse_C(EPWM_INFO*);
//
#define TBCLK 60000 // Don't change
#define STEP_UP_DOWN 0 // if 0, delay in PWM2 and PWM3 else delay in PWM1
#define FREQ 100 // KHZ
#define DB 200 // ns (better in multiples of 50ns)
#define DELAY 200 // ns (better in multiples of 50ns)
#define PULSE_MISS_FREQ 100 // Miss PULSE_MISS no. per PULSE_MISS_FREQ
#define PULSE_MISS 1 // No. of pulses to remove
EPWM_INFO epwm_info;
Uint16 LoopCount;
Uint16 ConversionCount;
Uint16 VoltageADC;
double actualVoltage=0;
void main(void)
{
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
InitSysCtrl();
// Step 2. Initialize GPIO:
// This example function is found in the DSP2803x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
// InitGpio(); // Skipped for this example
// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3
// These functions are in the DSP2803x_EPwm.c file
InitEPwm2Gpio();
InitEPwm3Gpio();
InitEPwm4Gpio();
InitEPwm5Gpio();
InitAdc();
AdcOffsetSelfCal();
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the DSP2803x_PieCtrl.c file.
InitPieCtrl();
// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in DSP2803x_DefaultIsr.c.
// This function is found in DSP2803x_PieVect.c.
InitPieVectTable();
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.EPWM2_INT = &epwm2_isr;
PieVectTable.EPWM3_INT = &epwm3_isr;
PieVectTable.ADCINT1 = &adc_isr;
EDIS; // This is needed to disable write to EALLOW protected registers
// Initialize all the Device Peripherals:
// Not required for this example
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
epwm_info.TBPRD = TBCLK/(FREQ*2);
epwm_info.DB_Set = DB*3/50;
epwm_info.Delay_Set = DELAY*3/50;
epwm_info.Duty_Set = epwm_info.TBPRD/2;
epwm_info.MAX_CMP = epwm_info.TBPRD;
epwm_info.MIN_CMP = 0;
InitEPwm4n5();
InitEPwm2();
InitEPwm3();
InitAdc();
AdcOffsetSelfCal();
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
// Enable CPU INT3 which is connected to EPWM1-3 INT:
IER |= M_INT3;
// Enable ADCINT1 in PIE
PieCtrlRegs.PIEIER1.bit.INTx1 = 1; // Enable INT 1.1 in the PIE
IER |= M_INT1; // Enable CPU Interrupt 1
// Enable EPWM INTn in the PIE: Group 3 interrupt 1-3
PieCtrlRegs.PIEIER3.bit.INTx2 = 1;
PieCtrlRegs.PIEIER3.bit.INTx3 = 1;
// Enable global Interrupts and higher priority real-time debug events:
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
// Configure ADC
// Note: Channel ADCINA1 will be double sampled to workaround the ADC 1st sample issue for rev0 silicon errata
EALLOW;
AdcRegs.ADCCTL1.bit.INTPULSEPOS = 1; //ADCINT1 trips after AdcResults latch
AdcRegs.INTSEL1N2.bit.INT1E = 1; //Enabled ADCINT1
AdcRegs.INTSEL1N2.bit.INT1CONT = 0; //Disable ADCINT1 Continuous mode
AdcRegs.INTSEL1N2.bit.INT1SEL = 2; //setup EOC2 to trigger ADCINT1 to fire
AdcRegs.ADCSOC0CTL.bit.CHSEL = 1; //set SOC0 channel select to ADCINA1(dummy sample for rev0 errata workaround)
AdcRegs.ADCSOC1CTL.bit.CHSEL = 1; //set SOC1 channel select to ADCINA1
AdcRegs.ADCSOC2CTL.bit.CHSEL = 2; //set SOC2 channel select to ADCINA2
AdcRegs.ADCSOC0CTL.bit.TRIGSEL = 5; //set SOC0 start trigger on EPWM1A, due to round-robin SOC0 converts first then SOC1, then SOC2
AdcRegs.ADCSOC1CTL.bit.TRIGSEL = 5; //set SOC1 start trigger on EPWM1A, due to round-robin SOC0 converts first then SOC1, then SOC2
AdcRegs.ADCSOC2CTL.bit.TRIGSEL = 5; //set SOC2 start trigger on EPWM1A, due to round-robin SOC0 converts first then SOC1, then SOC2
AdcRegs.ADCSOC0CTL.bit.ACQPS = 6; //set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
AdcRegs.ADCSOC1CTL.bit.ACQPS = 6; //set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
AdcRegs.ADCSOC2CTL.bit.ACQPS = 6; //set SOC2 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
EDIS;
// Assumes ePWM1 clock is already enabled in InitSysCtrl();
EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm1Regs.ETSEL.bit.SOCASEL = 4; // Select SOC from from CPMA on upcount
EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
EPwm1Regs.CMPA.half.CMPA = 0x0080; // Set compare A value
EPwm1Regs.TBPRD = 0xFFFF; // Set period for ePWM1
EPwm1Regs.TBCTL.bit.CTRMODE = 0; // count up and start
// Step 6. IDLE loop. Just sit and loop forever (optional):
for(;;)
{
LoopCount++;
__asm(" NOP");
}
}
void InitEPwm4n5()
{
EPwm4Regs.TBPRD = epwm_info.TBPRD; // Set timer period
EPwm4Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm4Regs.TBCTR = 0x0000; // Clear counter
EPwm5Regs.TBPRD = epwm_info.TBPRD; // Set timer period
EPwm5Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm5Regs.TBCTR = 0x0000; // Clear counter
// Setup TBCLK pwm4
EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
//EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Sync down-stream module
EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_IMMEDIATE; // Load registers ZERO
EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_IMMEDIATE;
// Setup TBCLK pwm5
EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm5Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
//EPwm5Regs.TBCTL.bit.PHSDIR = TB_UP; // Count DOWN on sync
//EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through
EPwm5Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm5Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm5Regs.CMPCTL.bit.SHDWAMODE = CC_IMMEDIATE; // Load registers imm
EPwm5Regs.CMPCTL.bit.SHDWBMODE = CC_IMMEDIATE;
// Setup compare PWM4
if(!STEP_UP_DOWN)
{
EPwm4Regs.CMPA.half.CMPA = epwm_info.Duty_Set;//150
}
else
{
EPwm4Regs.CMPA.half.CMPA = epwm_info.Duty_Set - epwm_info.Delay_Set; //138
}
// Setup compare pwm5
if(!STEP_UP_DOWN)
{
EPwm5Regs.CMPA.half.CMPA = epwm_info.Duty_Set;//150
}
else
{
EPwm5Regs.CMPA.half.CMPA = epwm_info.Duty_Set + epwm_info.Delay_Set; //162
}
// Set actions
EPwm5Regs.AQCTLA.bit.CAU = AQ_SET; //
EPwm5Regs.AQCTLA.bit.CAD = AQ_CLEAR; //
EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR; //
EPwm4Regs.AQCTLA.bit.CAD = AQ_SET; //
// Active High COMP PWMs - Setup Deadband
EPwm5Regs.DBCTL.bit.OUT_MODE = DBA_ENABLE;
EPwm5Regs.DBCTL.bit.POLSEL = DB_ACTV_HI;
EPwm5Regs.DBCTL.bit.IN_MODE = DBA_RED_DBB_FED;
EPwm5Regs.DBRED = epwm_info.DB_Set;
EPwm5Regs.DBFED = epwm_info.DB_Set;
EPwm4Regs.DBCTL.bit.OUT_MODE = DBA_ENABLE;
EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HI;
EPwm4Regs.DBCTL.bit.IN_MODE = DBA_RED_DBB_FED;
EPwm4Regs.DBRED = epwm_info.DB_Set;
EPwm4Regs.DBFED = epwm_info.DB_Set;
epwm_info.EPwmTimerIntCountP = 0;
epwm_info.EPwmTimerIntCountC = 0;
epwm_info.EPwmRegHandle4 = &EPwm4Regs; // Set the pointer to the ePWM module
epwm_info.EPwmRegHandle5 = &EPwm5Regs; // Set the pointer to the ePWM module
}
void InitEPwm2()
{
EPwm2Regs.TBPRD = epwm_info.TBPRD; // Set timer period
EPwm2Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter
// Setup TBCLK
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
//EPwm2Regs.TBCTL.bit.PHSDIR = TB_UP; // Count DOWN on sync
//EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow just to observe on the scope
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_IMMEDIATE;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_IMMEDIATE;
// Setup compare
if(!STEP_UP_DOWN)
{
EPwm2Regs.CMPA.half.CMPA = epwm_info.Duty_Set-epwm_info.Delay_Set; //138
EPwm2Regs.CMPB = epwm_info.Duty_Set+epwm_info.Delay_Set; //162
}
else
{
EPwm2Regs.CMPA.half.CMPA = epwm_info.Duty_Set;//150
EPwm2Regs.CMPB = epwm_info.Duty_Set;//150
}
// Set actions
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM2A on CAU
EPwm2Regs.AQCTLA.bit.CAD = AQ_SET; // Clear PWM2A on CAD
EPwm2Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Clear PWM2B on CAU
EPwm2Regs.AQCTLB.bit.CBD = AQ_SET; // Set PWM2B on CAD
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event
// Active Low complementary PWMs - setup the deadband
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm2Regs.DBCTL.bit.IN_MODE = DBA_RED_DBB_FED;
EPwm2Regs.DBRED = epwm_info.DB_Set;
EPwm2Regs.DBFED = epwm_info.DB_Set;
epwm_info.EPwmRegHandle2 = &EPwm2Regs; // Set the pointer to the ePWM module
}
void InitEPwm3()
{
EPwm3Regs.TBPRD = epwm_info.TBPRD; // Set timer period
EPwm3Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm3Regs.TBCTR = 0x0000; // Clear counter
// Setup TBCLK
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
//EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through
//EPwm3Regs.TBCTL.bit.PHSDIR = TB_UP; // Count DOWN on sync
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow just to observe on the scope
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_IMMEDIATE;
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_IMMEDIATE;
// Setup compare
if(!STEP_UP_DOWN)
{
EPwm3Regs.CMPA.half.CMPA = epwm_info.Duty_Set+epwm_info.Delay_Set; //162
EPwm3Regs.CMPB = epwm_info.Duty_Set-epwm_info.Delay_Set; //138
}
else
{
EPwm3Regs.CMPA.half.CMPA = epwm_info.Duty_Set;//150
EPwm3Regs.CMPB = epwm_info.Duty_Set;//150
}
// Set actions
EPwm3Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on CAU
EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM2A on CAD
EPwm3Regs.AQCTLB.bit.CBU = AQ_SET; // Clear PWM2B on CAU
EPwm3Regs.AQCTLB.bit.CBD = AQ_CLEAR; // Set PWM2B on CAD
EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_PRD; // Select INT on Period event
EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm3Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event
// Active Low complementary PWMs - setup the deadband
EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm3Regs.DBCTL.bit.IN_MODE = DBA_RED_DBB_FED;
EPwm3Regs.DBRED = epwm_info.DB_Set;
EPwm3Regs.DBFED = epwm_info.DB_Set;
epwm_info.EPwmRegHandle3 = &EPwm3Regs; // Set the pointer to the ePWM module
}
__interrupt void epwm2_isr(void)
{
// Update the CMP values
add_Miss_Pulse_P(&epwm_info);
// Clear INT flag for this timer
EPwm2Regs.ETCLR.bit.INT = 1;
// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
__interrupt void epwm3_isr(void)
{
// Update the CMP values
add_Miss_Pulse_C(&epwm_info);
// Clear INT flag for this timer
EPwm3Regs.ETCLR.bit.INT = 1;
// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
__interrupt void adc_isr(void)
{
VoltageADC = AdcResult.ADCRESULT1; //discard ADCRESULT0 as part of the workaround to the 1st sample errata for rev0
/*int i = 0;
while (i < 32 && Voltage1 <= temp_table[i])
{
i++;
}
double m = 1.0/(temp_table[i]-temp_table[i-1]);
double c = i - m*temp_table[i];
temperature = 4*(m*Voltage1 + c);*/
AdcRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //Clear ADCINT1 flag reinitialize for next SOC
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE
return;
}
int mp = 0;
int mc = 0;
int enablep = 0;
int enablec = 0;
void add_Miss_Pulse_P(EPWM_INFO *epwm_infoF)
{
if(epwm_infoF->EPwmTimerIntCountP == PULSE_MISS_FREQ - PULSE_MISS-1)
{
epwm_infoF->EPwmTimerIntCountP = 0;
mp=0;
enablep = 1;
//epwm_infoF->EPwmRegHandle2->CMPA.half.CMPA = epwm_info.MIN_CMP;
epwm_infoF->EPwmRegHandle2->CMPB = epwm_info.MAX_CMP;
epwm_infoF->EPwmRegHandle3->CMPA.half.CMPA = epwm_info.MAX_CMP;
//epwm_infoF->EPwmRegHandle3->CMPB = epwm_info.MIN_CMP;
//epwm_infoF->EPwmRegHandle4->CMPA.half.CMPA = epwm_info.MIN_CMP;
epwm_infoF->EPwmRegHandle5->CMPA.half.CMPA = epwm_info.MAX_CMP;
}
else if(enablep)
{
mp++;
if(mp == PULSE_MISS)
{
enablep=0;
//epwm_infoF->EPwmRegHandle2->CMPA.half.CMPA = (!STEP_UP_DOWN)? epwm_info.Duty_Set - epwm_info.Delay_Set : epwm_info.Duty_Set;
epwm_infoF->EPwmRegHandle2->CMPB = (!STEP_UP_DOWN)?epwm_info.Duty_Set + epwm_info.Delay_Set : epwm_info.Duty_Set;
epwm_infoF->EPwmRegHandle3->CMPA.half.CMPA = (!STEP_UP_DOWN)? epwm_info.Duty_Set + epwm_info.Delay_Set : epwm_info.Duty_Set;
//epwm_infoF->EPwmRegHandle3->CMPB = (!STEP_UP_DOWN)?epwm_info.Duty_Set - epwm_info.Delay_Set : epwm_info.Duty_Set;
//epwm_infoF->EPwmRegHandle4->CMPA.half.CMPA = (!STEP_UP_DOWN)? epwm_info.Duty_Set : epwm_info.Duty_Set - epwm_info.Delay_Set;
epwm_infoF->EPwmRegHandle5->CMPA.half.CMPA = (!STEP_UP_DOWN)? epwm_info.Duty_Set : epwm_info.Duty_Set + epwm_info.Delay_Set;
}
}
else
++epwm_infoF->EPwmTimerIntCountP;
return;
}
void add_Miss_Pulse_C(EPWM_INFO *epwm_infoF)
{
if(epwm_infoF->EPwmTimerIntCountC == PULSE_MISS_FREQ -PULSE_MISS - 1)
{
epwm_infoF->EPwmTimerIntCountC = 0;
mc=0;
enablec = 1;
epwm_infoF->EPwmRegHandle2->CMPA.half.CMPA = epwm_info.MIN_CMP;
//epwm_infoF->EPwmRegHandle2->CMPB = epwm_info.MAX_CMP;
//epwm_infoF->EPwmRegHandle3->CMPA.half.CMPA = epwm_info.MAX_CMP;
epwm_infoF->EPwmRegHandle3->CMPB = epwm_info.MIN_CMP;
epwm_infoF->EPwmRegHandle4->CMPA.half.CMPA = epwm_info.MIN_CMP;
//epwm_infoF->EPwmRegHandle5->CMPA.half.CMPA = epwm_info.MAX_CMP;
}
else if(enablec)
{
mc++;
if(mc == PULSE_MISS)
{
enablec=0;
//++epwm_infoF->EPwmTimerIntCountC;
epwm_infoF->EPwmRegHandle2->CMPA.half.CMPA = (!STEP_UP_DOWN)? epwm_info.Duty_Set - epwm_info.Delay_Set : epwm_info.Duty_Set;
//epwm_infoF->EPwmRegHandle2->CMPB = (!STEP_UP_DOWN)?epwm_info.Duty_Set + epwm_info.Delay_Set : epwm_info.Duty_Set;
//epwm_infoF->EPwmRegHandle3->CMPA.half.CMPA = (!STEP_UP_DOWN)? epwm_info.Duty_Set + epwm_info.Delay_Set : epwm_info.Duty_Set;
epwm_infoF->EPwmRegHandle3->CMPB = (!STEP_UP_DOWN)?epwm_info.Duty_Set - epwm_info.Delay_Set : epwm_info.Duty_Set;
epwm_infoF->EPwmRegHandle4->CMPA.half.CMPA = (!STEP_UP_DOWN)? epwm_info.Duty_Set : epwm_info.Duty_Set - epwm_info.Delay_Set;
//epwm_infoF->EPwmRegHandle5->CMPA.half.CMPA = (!STEP_UP_DOWN)? epwm_info.Duty_Set : epwm_info.Duty_Set + epwm_info.Delay_Set;
}
}
else
++epwm_infoF->EPwmTimerIntCountC;
return;
}
