TMS320F28035: Extra Delay between ADCSOCA and EOC Generation

Shiv Aishwarya Singh

Part Number: TMS320F28035

Hello,

I am trying to Generate SOC Event at EPWM2A CTR=CMPB . I am able to see ADCSOCA using GPIO at the right location. I also used another GPIO to see EOC generation using ADCINT1. But I see lot of delay between these Event. Ideally they should coincide. What I am missing? Also what does the width of ADCSOCA signify?

Regards,

Shiv

over 7 years ago

0 tlee over 7 years ago

TI__Guru 62975 points

Shiv,

Please compare your observations against the ADC timing diagrams in the datasheet and ADC user guide. What you are seeing might be reasonable depending on your ADC settings.

-Tommy

0 Shiv Aishwarya Singh over 7 years ago in reply to tlee

Intellectual 290 points

Hello Tommy,

I have set INTPULSEPOS to 0(Early Interrupt Pulse). So I believe my GPIO should become High with ADCSOCA. Also what does the width of ADCSOCA signify?

Regards,

Shiv

0 Devin Cottier over 7 years ago in reply to Shiv Aishwarya Singh

TI__Guru 60865 points

Hi Shiv,

Trigger to start of SOC (from above diagram) = 2 ADDCLKs

minimum S+H window = 7 ADCCLKs

ISR context switch latency = 14 SYSCLKs

Time in ISR to toggle the GPIO = ~4 SYSCLKs

If ADCCLK = 30MHz and SYSCLK = 60MHz then this gives about 9 * 33.3ns + 18 * 16.7ns = 600ns, which is pretty close to what you observe?

0 Shiv Aishwarya Singh over 7 years ago in reply to Devin Cottier

Intellectual 290 points

Hello Devin, Tommy,

what does the width of ADCSOCA signify?

Regards,
Shiv

0 Devin Cottier over 7 years ago in reply to Shiv Aishwarya Singh

TI__Guru 60865 points

Hi Shiv,

This is a pulse-stretched version of the ADCSOCA trigger event which can be used to trigger an external ADC.

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TMS320F28035: Extra Delay between ADCSOCA and EOC Generation