[FAQ] TMS320F28035: ADC Calibration and Total Unadjusted Error

Hi Stuart,

The first thing to look at is how we calculate total un-adjusted error (TUE).  From the ADC we usually consider gain error, offset error, INL, and DNL.  We also need to consider the error introduced by the ADC external reference.  We don't need to consider ADC channel-to-channel offset or gain error, since this is just a measure of how much the channels can vary from each other (the worst case specifications hold for all channels). 

The worst case ADC errors are usually independent (e.g. an ADC with worst case INL is unlikely to also have worst case gain error).  Because of this we don't directly add the worst case errors, since this would result in an an overly pessimistic TUE.  Instead, we add the errors using root-sum-squares.  

Before we consider calibration, here is a comparison of the raw TUE of C28x Piccolo series ADCs.  The specifications for F2803x, F2802x, F2806x, and F2805x are similar, so they don't all have their own table entry.  Note that in all C28x datasheets, the Min/Max ADC errors are specified including drift for voltage, temperature, and manufacturing process variation.  If a temperature coefficient is also provided, this isn't added on top of the worst case error (but instead gives some idea of how much of the error is due to temperature drift).  Also note that the F2803x (and similar devices mentioned above) require at least one-time offset self-calibration (we don't support factory offset trim).  All values in the table below are with external reference.

(1) Executing one-time self-calibration

The external reference gain error has has some assumptions.  This assumes a very good external reference solution.

For example, REF5030 has the following key specifications:

• Initial accuracy = 0.05% => 0.05%*4096 LSBs = 2.0 LSBs
• Temperature drift = 3ppm/deg. C => for standard temperature range (85C - 25C)*3ppm*4096 LSBs = 0.7 LSBs

And then OPA320 (which we recommend to drive the 12-bit reference on F2807x and F28004x) has

• Vos (max) = 150uV => 0.2 LSBs @ 3.0V

So the total worst case reference error can be estimated as sqrt(2^2 + 0.7^2 + 0.2^2) = 2.1 LSBs (and 1.0 LSBs is just a guess for typical reference error).  

Obviously if a different reference solution is used, the actual accuracy can also be calculated.  Getting something more accurate than the above example is possible, but will get very expensive very fast.  

Now to calibrate offset error all of these devices have an internal connection to VREFLO (no external channel required).  In the F2803x datasheet we specify +/-20LSBs with one-time offset calibration.  To get better performance we can calibrate periodically:

Procedure: Sample the internal VREFLO connection periodically.  Use these samples to adjust the ADC offset trim register accordingly.  Adjusting the HW trim register will adjust the ADC samples directly, so no additional SW post-processing is necessary.

Limitations: Channel-to-channel offset variation will limit how close we can get to perfect offset trim.  On F2803x, the channel-to-channel offset is specified as +/-4 LSBs.

Requirements:

• You can use the internal connection, so no external pin is required.  
• You also need to configure one of the SOCs to periodically sample the signal.  On F2803x, this can be an issue if you are already using all 16 SOCs.  There is also no way to automatically (in the SOC configuration) switch between the internal VREFLO connection and the external pin.  These can both be overcome by swapping some of the SW settings in the ADC ISR and then triggering more samples 

Note: If the offset error is negative, the ADC conversion of VREFLO will read 0 and you won't know if the true offset error is -1 or something like -20.  If you are periodically calibrating offset error on-line, the easiest way to handle this is to trim towards an offset error of +1 instead of 0.  If the offset error is large and negative, successive rounds of calibration will eventually drive the offset error to +1.  You can then either accept the extra 1 LSBs of error, or you can use the CPU to post-process the results.  ADC range will be reduced by 1 LSB.  

Calibrating gain error is a little more involved. 

Procedure: Provide a single calibration voltage near the full-scale range. Since we already have an internal method to calibrate offset error, we don't need to do 2-point gain trim.  Practically, using more calibration points will help average-out INL errors.  This calibration voltage should be sampled periodically.  The CPU can then post-process the ADC results to remove the gain error.    

Limitations: 

The error from sampling the calibration signal comes from a few sources:

• Channel-to-channel gain variation => +/-4 LSBs on F2803x
• INL +/-4 LSBs on F2803x
• Error in the calibration source => probably not better than +/2.1 LSBs
• Offset error has a complicated effect, but mostly cancels out...if offset error is positive, the calibration voltage reads high and the gain calibration will cancel out the offset error at the calibration point (near full-scale-range).    

The best we can do for sampling error of the calibration voltage is therefore sqrt(4^2 + 4^2 + 2.1^2) =  6.0LSBs

The error at full scale range scales up based on where the calibration was done.  So if the FSR is 3.0V and the calibration voltage is 2.5V, the total gain error would therefore be 3.0V/2.5V * 6.0LSBs = 7.2 LSBs.

Note: Because of the above, we want to do calibration as close to full-scale as possible.  However, there needs to be enough space between full-scale and the calibration voltage to allow for any uncalibrated drift.  For F2803x, the natural gain error is 40 LSBs = 30mV @ 3.0V VREFHI.  

Requirements: 

• An external channel to sample the calibration voltage
• You also need to configure one of the SOCs to periodically sample the signal.
• The CPU has to scale all the ADC results via post-processing...no HW method to compensate for gain error is available.  
• The external calibration voltage needs to be accurate.  This can be achieved two ways:
  • A second precision voltage IC (see the first diagram below)
    • In this case, an op-amp is probably not needed to drive the ADC pin (just use a large capacitor directly on the ADC pin)
    • Calibration will also take care of any gain error in the external reference IC, so that IC can be a cheaper and less accurate IC in this case (within reason...it depends how much space you have between the calibration voltage and the full-scale-range).  
  • A precision voltage divider from the VREFHI reference IC (see the second diagram below)
  • You definitely need to use matched resistors in a single package to get good performance

We can now fill back into the table the errors for F2803x with on-line calibration:

(1) Executing periodic re-calibration

(2) Error Included in ADC gain calibration

Some other notes:

• Doing the calibration periodically should take care of any internal ADC temperature coefficients.  
  • Calibration should be done fast enough to deal with the expected rate of thermal change in the system.  Usually re-calibrating a couple times per-second should be plenty fast.
  • (You still need to consider the external temperature coefficients of your calibration voltage)
•  The DC code-spread for this ADC is roughly 4 LSBs.  When you take calibration readings, it is best to take many points and average.  I'd recommend averaging 256 points or more.
  • (For every 4x oversampling, you gain 1 bit of SNR, so 4^4 = 256 samples results in noise of about 4 LSBs * (0.5^4) = 0.25 LSBs of noise. 64 sample averages would give you about 0.5 LSBs of noise.)   
• It's important to get good settling on the ADC inputs, because settling error is random or cross-talk from previous samples.  This can't be corrected.  This also applies to your calibration input, so ensure settling much less than 1 LSBs on these calibration inputs.