Part Number: LAUNCHXL-F28377S
Tool/software: Code Composer Studio
Hi,
I have a question about “2837x_rfft_adc_rt”:
I need to increase my sample rate analog to digital from 100ksps to 500 Ksps,
changing the following parameter in the "example_setup.h" is enough?
#define ADC_SAMPLING_FREQ 100000.0L
or other changes in the project is necessary.
Thank you for your help.
Best regards,
Amin
Dear Whitney,
In this project(2837x_rfft_adc_rt) there is a square wave generator, I want to control the start and stop point of each pulses and sampling the analog signal in other ADC channel at the same time.
How can I generate a certain number of square wave, for example 1 square wave? I need to have the “start” and “end” points of each square wave in the project and run ADC pin_A0 from start point to end point of each square wave.
In other words, If we assume “A” is the start point of each pulse period, and the end point of each period is point “B”, then:
start point of ADC= at the beginning of square wave(point A)
end point of ADC= at the end point of square wave(point B)
How do I synchronize the ADC channel and Square wave generator?
Thank you and best regards,
Amin
Whitney,
Thank you very much for your help.
My goal is ADC sampling at the rising edge to rising edge of the next pulse.
Because I need to have the samples(ADC pin) corresponding to each pulse(generated by PWM),
As it is seen in Fig., Sampling begins at the beginning of each pulse to the beginning of the next pulse(this will not be done for all pulses), and then split the samples on the falling edge of the pulse.
I'm not saying stop function(said before post "the end point"), my goal is just find the location of the rising edge of each pulses.
Thanks and Best regards,
Amin
Hi Whitney,
With your suggestion, signal is not produced in the particular edge and it is variable.
An example for clarification:
Assume that we have two channels simultaneous ADC,
ADC1 connected to a pulse generator with fix frequency and duty cycle(the pwm channel connected to a device to generate signal ’S’).
ADC2 connected to an arbitrary signal ’S’.
Then we have two vectors and we need find the following index(i,j,k,l, …) to separate the signal on the second channel(this method is complex).
Now, instead of two channels simultaneous ADC, I have a PWM generator (ePWM2) and an ADC channel(ePWM1).
If I know the pulse is generated at the rising edge and ADC start to sampling at the same time,
since the pulse frequency is fixed, I can separate the samples in a fixed index.
I need to always generate pulses in a special way(rising or falling edge) and start sampling at this time.
Thanks and best regards,
Amin
Hi Whitney,
The main function is as follows:
Breakpoint placed in the while(1) loop,
Please see this function: __interrupt void adcaIsr()
//############################################################################# //! \file /2837x_RFFT_ADC/main.c //! //! \brief Demo code for the 512 pt real-time RFFT with the input from the ADC //! \author Vishal Coelho (Modified the original) //! \date 03/26/2015 //! //! This program shows how to compute a real FFT with 12-bit real-time ADC //! input and associated spectrum magnitude, phase. EPWM1 and 2 are setup //! such that EPWM2 outputs a square wave at a frequency 10 times slower //! than EPWM1; EPWM1 serves as the sample clock to the ADC which will //! sample EPWM2A (pin 53) through channel A0 (pin 09) and then run the FFT. //! The real time FFT is computed frame-by-frame. Once a entire frame is //! filled up in the ADC ISR, it sets off a flag to start the FFT. The //! flag is reset once the computation is complete //! //! \note This example uses the F2837xD controlCARD Rev1.1 //! \note The input buffer must be aligned to a 2N word boundary, N being the //! size of the real FFT. The user may choose to use an alternative routine, //! RFFT_adc_f32u(), if alignment is not possible (or not desired). In that //! case, the section alignment #pragma can be commented. However, using this //! function will reduce cycle performance of the algorithm. //! // Group: C2000 // Target Family: F2837x // //############################################################################# // $TI Release: C28x Floating Point Unit Library V1.50.00.00 $ // $Release Date: May 22, 2017 $ // $Copyright: Copyright (C) 2017 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //############################################################################# //***************************************************************************** // includes //***************************************************************************** #include "fpu_rfft.h" // Main include file #include "math.h" #include "examples_setup.h" //! //! \addtogroup RFFT_EXAMPLES Real FFT of the ADC Input (Real-Time) // @{ //***************************************************************************** // defines //***************************************************************************** #define RFFT_STAGES 9 #define RFFT_SIZE (1 << RFFT_STAGES) #define F_PER_SAMPLE (ADC_SAMPLING_FREQ/(float)RFFT_SIZE) #define USE_TEST_INPUT 1 // If not in test mode, be sure to exclude signal.asm // from the build #define EPSILON 0.1 //***************************************************************************** // globals //***************************************************************************** #ifdef __cplusplus #pragma DATA_SECTION("RFFTdata1") #else #pragma DATA_SECTION(RFFTin1Buff,"RFFTdata1") #endif //__cplusplus //! \brief FFT Calculation Buffer //! \note The input buffer needs to be aligned to an 2N word boundary //! \note If the number of FFT stages is odd, the result of the FFT will //! be written to this buffer //! \note this buffer takes N 12-bit ADC input, hence its defined as an //! unsigned int array, but the FFT algorithm ping-pongs between input/ //! output buffers each stage, therefore this buffer needs to be able //! to accommodate N floats and should be of size 2*RFFT_SIZE uint16_t RFFTin1Buff[2*RFFT_SIZE]; #ifdef __cplusplus #pragma DATA_SECTION("RFFTdata2") #else #pragma DATA_SECTION(RFFTmagBuff,"RFFTdata2") #endif //__cplusplus //! \brief Magnitude Calculation Buffer //! float RFFTmagBuff[RFFT_SIZE/2+1]; #ifdef __cplusplus #pragma DATA_SECTION("RFFTdata2") #else #pragma DATA_SECTION(RFFTmagBuff,"RFFTdata2") #endif //__cplusplus //! \brief Phase Calculation Buffer //! float RFFTphaseBuff[RFFT_SIZE/2]; #ifdef __cplusplus #pragma DATA_SECTION("RFFTdata3") #else #pragma DATA_SECTION(RFFToutBuff,"RFFTdata3") #endif //__cplusplus //! \brief FFT Calculation Buffer //! \note If the number of FFT stages is even, the result of the FFT will //! be written to this buffer //! float RFFToutBuff[RFFT_SIZE]; #ifdef __cplusplus #pragma DATA_SECTION("RFFTdata4") #else #pragma DATA_SECTION(RFFTF32Coef,"RFFTdata4") #endif //__cplusplus //! \brief Twiddle Factors //! float RFFTF32Coef[RFFT_SIZE]; //! \brief RFFT_ADC_F32_STRUCT object //! RFFT_ADC_F32_STRUCT rfft_adc; //! \brief Handle to the RFFT_ADC_F32_STRUCT object //! RFFT_ADC_F32_STRUCT_Handle hnd_rfft_adc = &rfft_adc; //! \brief RFFT_F32_STRUCT object //! RFFT_F32_STRUCT rfft; //! \brief Handle to the RFFT_F32_STRUCT object //! RFFT_F32_STRUCT_Handle hnd_rfft = &rfft; //! \brief Flag to signal the ADC has finished sampling, and storing, //! N points in the FFT input buffer //! volatile uint16_t flagInputReady = 0; //! \brief Index into the FFT input buffer //! volatile uint16_t sampleIndex = 0; //***************************************************************************** // Function Prototypes //***************************************************************************** __interrupt void adcaIsr(); //***************************************************************************** // function definitions //***************************************************************************** //! //! \brief main routine for the 512-sample RFFT ADC example //! \return returns a 1 //! //! This program shows how to compute the real FFT, magnitude and phase of //! data from the 12-bit ADC input. The input buffer must be aligned to a //! 2N word boundary if using RFFT_f32. //! Data section alignment (#pragma ...) is not necessary for RFFT_adc_f32u //! but necessary when running RFFT_adc_f32. However, using the unaligned //! version will reduce cycle performance of the algorithm. //! //! The minimum number of stages is 3. When the number of stages is more //! than 9, the quantization error would be significant and not recommended. //! This example will sample an EPWM channel over an ADC channel and run the //! RFFT on a real signal. //! //! RFFT_F32_STRUCT is a structure defined as: //! //! typedef struct { //! float *InBuf; //! float *OutBuf; //! float *CosSinBuf; //! float *MagBuf; //! float *PhaseBuf; //! uint16_t FFTSize; //! uint16_t FFTStages; //! } RFFT_F32_STRUCT; //! //! RFFT_ADC_F32_STRUCT is defined as: //! typedef struct { //! uint16_t *InBuf; //! void *Tail; //! } RFFT_ADC_F32_STRUCT; //! //! ASSUMPTIONS: //! //! -# OutBuf of RFFT_F32_STRUCT has to be passed to Tail of //! RFFT_ADC_F32_STRUCT //! -# Input signal is stored in Signal.asm //! -# FFTSize must be a power of 2 (32, 64, 128, etc) //! -# FFTSize must be greater or equal to 32 //! -# FFTStages must be log2(FFTSize) //! -# InBuf, OutBuf, CosSinBuf are FFTSize in length //! -# Magnitude buffer is FFTSize/2+1 in length //! -# Phase buffer is FFTSize/2 in length //! //! Watch Variables: //! //! -# InBuf(RFFT_ADC_F32_STRUCT) Input buffer //! -# InBuf(RFFT_F32_STRUCT) Not used //! -# Tail Stored the address of OutBuf //! -# OutBuf Output buffer //! -# CosSinBuf Twiddle factor buffer //! -# MagBuf Magnitude buffer //! -# PhaseBuf Phase buffer //! -# j Index of normalized digital frequency component //! -# freq Real analog frequency of raw signal //! //! External Connections: //! Connect A0 (pin 9) to EPWM2A (pin 53) on the F2837x controlCARD. Refer to the //! board schematic for pin positioning. //! \note The ADC will sample a 50% duty cycle 1KHz wave (EPWM2A) at 100KHz //! and run the FFT on it. Since the input is a square wave, you will //! see the fundamental frequency, 1KHz, at the 5th bin //! (5*fs/N = 5*100K/512 = 976.5) and all its odd harmonics. Since the sampled //! waveform is not an integer multiple of the FFT_SIZE, you will see some //! spectral leakage, a portion of the fundamental will leak into the 6th bin. //! One way to overcome this is to window the input before running the FFT on //! it. //! int16_t main(void) { // Locals uint16_t i, j; float freq = 0.0; #ifdef FLASH EALLOW; Flash0EccRegs.ECC_ENABLE.bit.ENABLE = 0; memcpy((uint32_t *)&RamfuncsRunStart, (uint32_t *)&RamfuncsLoadStart, (uint32_t)&RamfuncsLoadSize ); FPU_initFlash(); #endif //FLASH FPU_initSystemClocks(); FPU_initEpie(); // Setup ADC-A FPU_initADCA(); //Setup EPWM1A as the sampling clock, EPWM2A as the signal to be //sampled FPU_initEPWM(); //Map ISR functions EALLOW; PieVectTable.ADCA1_INT = &adcaIsr; //function for ADCA interrupt 1 EDIS; //Enable global Interrupts and higher priority real-time debug events: PieCtrlRegs.PIEIER1.bit.INTx1 = 1; //Enable ADC1INT IER |= M_INT1; //Enable group 1 interrupts EINT; // Enable Global interrupt INTM ERTM; // Enable Global realtime interrupt DBGM //Start up the EPWMs FPU_startEPWM(); //Link the RFFT_ADC_F32_STRUCT to RFFT_F32_STRUCT. Tail pointer //of RFFT_ADC_F32_STRUCT is passed to the OutBuf pointer of //RFFT_F32_STRUCT hnd_rfft_adc->Tail = &(hnd_rfft->OutBuf); hnd_rfft->FFTSize = RFFT_SIZE; //FFT size hnd_rfft->FFTStages = RFFT_STAGES; //FFT stages hnd_rfft_adc->InBuf = &RFFTin1Buff[0]; //Input buffer (12-bit ADC input) hnd_rfft->OutBuf = &RFFToutBuff[0]; //Output buffer hnd_rfft->CosSinBuf = &RFFTF32Coef[0]; //Twiddle factor hnd_rfft->MagBuf = &RFFTmagBuff[0]; //Magnitude output buffer hnd_rfft->PhaseBuf = &RFFTphaseBuff[0]; //Phase output buffer RFFT_f32_sincostable(hnd_rfft); //Calculate twiddle factor for (i=0; i < RFFT_SIZE; i++){ RFFToutBuff[i] = 0; //Clean up output buffer } for (i=0; i <= RFFT_SIZE/2; i++){ RFFTmagBuff[i] = 0; //Clean up magnitude buffer } for (i=0; i < RFFT_SIZE/2; i++){ RFFTphaseBuff[i] = 0; //Clean up phase buffer } while(1){ while(flagInputReady == 0){}; // Wait on ADC ISR to set the flag // before proceeding RFFT_adc_f32(hnd_rfft_adc); // Calculate real FFT (12-bit ADC input) <----------------------------BreakPoint flagInputReady = 0; // Reset the flag #ifdef __TMS320C28XX_TMU__ //defined when --tmu_support=tmu0 in the project // properties RFFT_f32_mag_TMU0(hnd_rfft); //Calculate magnitude RFFT_f32_phase_TMU0(hnd_rfft); //Calculate phase #else RFFT_f32_mag(hnd_rfft); //Calculate magnitude RFFT_f32_phase(hnd_rfft); //Calculate phase #endif //__TMS320C28XX_TMU__ //Find out the maximum frequency component of signal frequency //component signal. This algorithm is only used for finding frequency //of one component frequency signal; in this example it gives the //fundamental frequency of the sampled square wave j = 1; freq = RFFTmagBuff[1]; for(i=2;i<RFFT_SIZE/2+1;i++){ //Looking for the maximum component of frequency spectrum if(RFFTmagBuff[i] > freq){ j = i; freq = RFFTmagBuff[i]; } } //Converting normalized digital frequency to real analog frequency //f = m * fs/N // where m is the bin with the maximum value, fs the sampling // frequency and N the number of points in the FFT freq = F_PER_SAMPLE * (float)j; } // Execution never reaches this point return 1; } // End of main //! \brief ADC Interrupt Service Routine //! The ISR will store each sampled value in the FFT buffer, and //! raise the flag once the buffer is full //! __interrupt void adcaIsr() { RFFTin1Buff[sampleIndex++] = AdcaResultRegs.ADCRESULT0; if(sampleIndex == (RFFT_SIZE - 1) ){ sampleIndex = 0; flagInputReady = 1; EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; //<---------------------------------------new EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;//<---------------------------------------new EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET;//<---------------------------------------new EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;//<---------------------------------------new } AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; } // @} //addtogroup // End of file
results of run the program( with Resume (F8)) several times and displayed on an oscilloscope:
Thank you.
Regards,
Amin
I changed the code,
void FPU_initEPWM(void)
{
CpuSysRegs.PCLKCR2.bit.EPWM1 =1; // Enable EPWM1 clocks
CpuSysRegs.PCLKCR2.bit.EPWM2 =1; // Enable EPWM1 clocks
//Enable EPWM GPIOs
InitEPwm1Gpio();
InitEPwm2Gpio();
EALLOW;
// EPWM clock divider set to /2
ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = 1;
// Turn off the EPWM clock
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
// Disable SOC on A group
EPwm1Regs.ETSEL.bit.SOCAEN = 0;
// Select SOC on up-count
EPwm1Regs.ETSEL.bit.SOCASEL = 4;
// Generate pulse on 1st event
EPwm1Regs.ETPS.bit.SOCAPRD = 1;
// Set compare A value to 2000 counts
EPwm1Regs.CMPA.bit.CMPA = EPWM1_DUTY_CYCLE;
// Set period to 4000 counts
EPwm1Regs.TBPRD = EPWM1_PERIOD;
// freeze counter
EPwm1Regs.TBCTL.bit.CTRMODE = 3;
//enable SOCA
EPwm1Regs.ETSEL.bit.SOCAEN = 1;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = EPWM_HSPCLKDIV;
// Disable SOC on A group
EPwm2Regs.ETSEL.bit.SOCAEN = 0;
// Set compare A value to 10000 counts
EPwm2Regs.CMPA.bit.CMPA = EPWM2_DUTY_CYCLE;
// Set period to 20000 counts
EPwm2Regs.TBPRD = EPWM2_PERIOD;
// freeze counter
EPwm2Regs.TBCTL.bit.CTRMODE = 3;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = EPWM_HSPCLKDIV;
// Clear PWM1A on Zero
/* EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;
EPwm1Regs.AQCTLA.bit.PRD = AQ_CLEAR;
// Clear PWM2A on Zero
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;
EPwm2Regs.AQCTLA.bit.PRD = AQ_CLEAR;*/
EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET;
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET;
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EDIS;
}
the problem is that the stored values on the RFFTin1Buff is a variable in the time
I need to start pulses are always the same.
Regards,
Amin
Thank you for your help. I changed the code, BreakPoint as follow:
while(1){
while(flagInputReady == 0){};
RFFT_adc_f32(hnd_rfft_adc); // Calculate real FFT (12-bit ADC input) <----------------------------BreakPoint
...
}
for first run, the result is good and, RFFTin1Buff is:
But I do not see the same results in the next runs, All indices in the RFFTin1Buff[] are shifted to RFFTin1Buff[0].
Regards,
Amin