TMS320F28377D: using CPU1 and CPU2 to control 2x separate converters?

Hi Leonardo,

On this device, CPU1 and CPU2 have same capabilities except some device initialization and GPIO setup control are with CPU1 only (which is initialization part). So you should be able to share the load between CPU1 and CPU2. In fact each CPU subsystem have it's own CLA also which can be used to share the load.

Regards,

Vivek Singh

Hi Leo,

We have reduced specifications when the ADCs are operated asynchronously (see the performance specifications in the datasheet). This performance degradation is much less significant with the ZWT package.

If your two converters would trigger the ADCs asynchronously / not in lock-step, then you might want to use the ZWT package if possible.

Hi Devin,

thanks for your reply. I am not sure about the ZWT package... My configuration is the following: I have 2x dc-dc converters which I would like to drive and control separately on CPU1 and CPU2.

Each converter has 4 adc signals. Converter #1 is using channel A2, B4, C2, D0 and converter #2 will use for instance A3, B5, C3, D1. I have not connected converter #2, yet and at the moment I am using only converter #1. As it stands the adc conversions A2, B4, C2, D0 occur in parallel, and they are started by an EPWM6 CTR = 0 pulse; when the adc conversions are done, an adc interrupt is triggered. Inside the interrupt the control and the PWM CMP update are executed.

If now I drive converter #1 from EPWM6 in CPU1 and converter # 2 from EPWM7 in CPU 2, (with EPWM6 and 7 identical) I would like to to the following:

1) have EPWM6 CTR = 0 event to start adc conversion on A2, B4, C2, D0
2) have the same EPWM6 = 0 event to trigger adc conversion on A3, B5, C3, D1
3) when the adc conversions (A2, B4, C2, D0 ) are done, then trigger an adc interrupt to CPU1, and run controller and pwm update on converter #1
4) when the adc conversions (A3, B5, C3, D1) are done, then trigger an interrupt on CPU2, and run controller and pwm update on converter #2

5) make sure that at the next EPWM6 CTR = 0 event, points 1 to 4 above will be repeated, in the same order, i.e. starting from adc A2, B4, C2, D0 and then moving onto A3, B5, C3, D1

Would this be possible? How could I set up the adc conversion to always perform the conversion in the order of point 1) and 2) above?

Hope my question makes sense...

Thanks a lot for your help.

Leo

Hi Leo,

Yeah, you can definitely do this. Just have ePWM6 CTR = 0 be the trigger for all 8 SOCs. All 4 CPU1 channels should use SOC0 and all 4 CPU2 channels should use SOC1. Set CPU1 to have an ISR from end-of-conversion on SOC0, ADCA. Set CPU2 to have an ISR from end-of-conversion on SOC1. CPU1 ISR reads conversion result 0 from all 4 ADCs while CPU2 ISR reads conversion result 1 from all 4 ADCS.

You could also try and do this using a CLA task trigger instead of a CPU ISR if you want to offload one (or both) control calculations to the CLA.

Note: all 4 simultaneous CPU1 samples should use the same ACQPS setting / S+H duration (and same for the 4 simultaneous CPU2 ACQPS settings).