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LAUNCHXL-F28379D: ADC sampling: 1MHz sampling is smooth but 100KHz and 10KHz sampling is bad

Tom Liang
Intellectual 510 points
Part Number: LAUNCHXL-F28379D

I just ran into this weird situation. I wrote my code and tested it with 1MHz sine wave input and the result was good. But when I changed the input to 100KHz sine wave, the ADC plot is really bad. 

So I switched back to the example code "adc_ex2_soc_epwm.c" and tested it. It has the same problem. I will attach some graph I obtained from my tests:

1st plot: 1MHz sine wave, 1Vpp, 1V DC offset

2nd plot: 1st plot zoomed in

3rd plot: 100KHz sine wave, 1Vpp, 1V DC offset

4th plot: 10KHz sine wave, 1Vpp, 1V DC offset

5th plot: 1KHz sine wave, 1Vpp, 1V DC offset

I don't understand why the ADC can sample 1MHz nicely but it cannot handle 100KHz and 10KHz. 

another problem I don't get understand is: when I sampled 1MHz, I can get around 8 samples per cycle (so it's like 8MSPS), but I only got about 5 samples per cycle when I sampled 1KHz (so it's like 5KSPS).

I don't know if my method to calculate ADC sampling rate is correct. 

  • 0
    TI__Mastermind 27355 points
    Hi Tom,

    It looks like it could be an aliasing problem where your ADC sampling rate is not high enough. The sampling rate is set by the ePWM period.
    Can you share how you've configured the ePWM?

    Thanks,
    Sahin
  • 0 in reply to Sahin Okur
    Intellectual 510 points 
    /*Hi Sahin. Thanks for replying.
    I just used the example code; the ePWM initialization is shown below: */

    void initEPWM(void)
{
    //
    // Disable SOCA
    //
    EPWM_disableADCTrigger(EPWM1_BASE, EPWM_SOC_A);

    //
    // Configure the SOC to occur on the first up-count event
    //
    EPWM_setADCTriggerSource(EPWM1_BASE, EPWM_SOC_A, EPWM_SOC_TBCTR_U_CMPA);
    EPWM_setADCTriggerEventPrescale(EPWM1_BASE, EPWM_SOC_A, 1);

    //
    // Set the compare A value to 2048 and the period to 4096
    //
    EPWM_setCounterCompareValue(EPWM1_BASE, EPWM_COUNTER_COMPARE_A, 0x0800);
    EPWM_setTimeBasePeriod(EPWM1_BASE, 0x1000);

    //
    // Freeze the counter
    //
    EPWM_setTimeBaseCounterMode(EPWM1_BASE, EPWM_COUNTER_MODE_STOP_FREEZE);
}

    so if my EPWMCLK is 100MHz and the time base period is 4096, my ADC sampling rate is 24.4KHz?

  • 0 in reply to Sahin Okur
    Intellectual 510 points
    I just found the formula to calculate PWM period and frequency in the datasheet. It's making some sense. My TBCLK is 50MHz, and TBPRD is 4096, so the PWM frequency is 12.2KHz; therefore, it's an aliasing problem. This explains the problems of 100KHz and 10KHz.
    But I still don't get 1MHz case, like if the frequency to trigger ADC sampling is only 12.2KHz, how can it sample 1MHz and the graph is so smooth.
  • 0 in reply to Tom Liang
    TI__Mastermind 27355 points
    Hi Tom,

    The waveform can sometimes still be recovered even if it's being sampled well below the Nyquist rate, however it should be at a much lower frequency. In our case, I believe the aliased frequency would be (12.2k-82)*1Mhz = 728Hz, which should result in about 16 samples per cycle instead of 9. Can you confirm whether you're running the PWM in up-count or up-down mode? Running in up-down count mode would explain why we're only seeing 9 samples.

    Also, once you increased the sampling rate were you able to correctly see the waveforms?

    Best,
    Sahin
  • 0 in reply to Sahin Okur
    Intellectual 510 points
    count up mode.
    yes, the waveform looks better if I decrease the TBPRD (increase the sampling rate).