CCS/TMS320F28335: About ADCRESEXT and ADC error!

Thanks Tommy.

The signal source is an op-amp output (0.5v to about 1.5v) range. it is an error signal. I am filtering it as well with an RC (30ohms and 2.2microFarad).

I am using (view->memory->data->32 bit binary->&AdcRegs.ADCRESULT0) to monitor the results. This is my initial thread

https://e2e.ti.com/support/microcontrollers/c2000/f/171/p/609821/2247353#2247353

what do you think? What should I do? What about the adcresext?

By the way, I have another small question about adc to epwm operation, since the output of the 12bit adc is btw 0 and 4095 when I have a TBPRD greater than 4095 say 7500, at 100% duty cycle corresponding to cmpa of 7500, how does the 4095 from the adc translate to cmpa's 7500?

I hope my ques are not too much......

David

David,

According to the schematics that you linked, the ADCRESEXT is already populated:

For the ADC results, I recommend that you monitor the AdcMirror.ADCRESULTn registers using 16-bit native words so that there are fewer confounding factors to consider.

If you continue to see wild fluctuations in conversions, I would recommend that you step back and try the adc_soc controlSUITE example while driving in a static voltage.  There is too much going on for effective debug.

The ADC 12b full-scale range is independent of the EPWM 16b registers.

-Tommy

Thank you for your response.

1a. Initially I shorted ADCREFIN to U29 through JP1, I felt diagram A-4 in c2000.spectrumdigital.com/.../ezdspf28335c_techref.pdf expected me to connect it that way so that power from VDDA_3v3 will get to ADCREFIN, maybe I misinterpreted it. I disconnected it and ran the ADCLO tests again but I didn't see much difference until I increased ACQ_PS to 15 as you advised, now I am getting [16,15,24,15,12...] and [6,6,3,3,5...] from ADCINA4 and ADCINA3 resp. I feel if I subtract an offset of about 18 and 5 resp. I will be okay, am I correct?

1b. Unlike in 1a where I had just connected ADCLO through a 10ohm resistor, I decided to use the RC this time. And I grounded the C through AGND (1 kohm resistor + ground) to a the ground of a power supply at 0v. I got the following [11,37,29,0,0...] and [0,12,16,8,0...]. It seems the ground has messed it up somehow. Anyway, what do you think or have I carried out the test wrongly?

2. For the 1v test, my output was from an op-amp and it went through an RC (10ohms and 2.2microFarad). I got the following [2176,2138,2160,2166,2162...] and [2174,2129,2141,2157,2150...]. I measured the voltage across the adc inputs, I got 1v when I measure it with respect to ground and 0.7v when I measured it with respect to AGND. The resistor in the analogue ground is consuming about 0.3v. I got the idea of how to setup the analogue ground from A-11 in the above link. Is my AGND setup even correct? Am I supposed to get voltage drop across the AGND? Anyway, even at 0.7v the digital values which I got as above doesn't make any sense?

What do you think?

David.

David Bamgboje said:

1b. Unlike in 1a where I had just connected ADCLO through a 10ohm resistor, I decided to use the RC this time. And I grounded the C through AGND (1 kohm resistor + ground) to a the ground of a power supply at 0v. I got the following [11,37,29,0,0...] and [0,12,16,8,0...]. It seems the ground has messed it up somehow. Anyway, what do you think or have I carried out the test wrongly?

You should be sampling ADCLO directly with no resistance.  There is a Sampling Capacitor (Ch) that must be charged (or discharged) to the ADCIN voltage within the ACQ_PS sampling window.  Adding series resistance (Rs) will slow down the charging speed:

David Bamgboje said:

2. For the 1v test, my output was from an op-amp and it went through an RC (10ohms and 2.2microFarad). I got the following [2176,2138,2160,2166,2162...] and [2174,2129,2141,2157,2150...]. I measured the voltage across the adc inputs, I got 1v when I measure it with respect to ground and 0.7v when I measured it with respect to AGND. The resistor in the analogue ground is consuming about 0.3v. I got the idea of how to setup the analogue ground from A-11 in the above link. Is my AGND setup even correct? Am I supposed to get voltage drop across the AGND? Anyway, even at 0.7v the digital values which I got as above doesn't make any sense?

How is VREFLO connected on your setup?  Is R6 populated on the eZdsp?

How are the op-amps powered?  What is the ground reference for your op-amp circuit relative to the eZdsp?  How is your input signal grounded?

David Bamgboje said:

I saw somewhere in this forum that whether one is using internal or external reference, one should ground the ADCREFM (I think this is VREFLO) and ADCREFP through a 2.2microFarad capacitor. So, I am also doing that.

The handling of ADCREFP and ADCREFM pins look the same to me in the datasheet whether using internal or external reference.  I see different handling of ADCREFIN.

You should be using the on-board C11 and C12 capacitors only.

David Bamgboje said:

I am setting up the ADC inputs according to the figure 4 of this material www.ti.com/.../spraap6a.pdf my Rin is 10ohms and my Cin is 10pF. I am using a dual op-amp with +12 and -12v supply. It is a difference op-amp in which I have 0.1(v2-v1) for the 2 op-amps with v1 as ground. And since I am using a single ground all through (i.e power supply ground) I simply connected that ground to the adc.

This sounds ok.  10Ω is relatively low resistance, but you may need to increase the ACQ_PS value if the conversions are not repeatable.

David Bamgboje said:

I don't think the R6 is populated. I simply connected a 1k ohm resistor as R6 and connected it to ground to make up AGND.

I would recommend populating R6 using a 0Ω resistor for baseline debug.  1kΩ is too large of a resistance.

David Bamgboje said:

By the way, I am not really using the diagram you pasted, I am using the one with the op-amp and that one has Rin and Cin so If i put together what you said about not sampling ADCLO through a resistor which in my case is RIN, do you mean I should only use the Rin&Cin for analogue inputs not for ADCLO sampling test. If so, I will do that but I am still left with the conversion issue........

The diagram is the ADC Input Impedance Model from the datasheet.  It is meant for the user to understand the electrical characteristics of the ADC input pin.  For example, you can run SPICE simulations using that model to calculate the required ACQ_PS value for your system.

Thank you for not getting tired of my questions.

I have basically done all you have said. I have taken your recommendations and I have made the necessary changes. Now I have just 2 main connections.

1. Adclo connected directly to ground. (R6 is poupulated, I missed that earlier).

2. RC filter (10ohm & 10pf) between adcin and input voltage.

I have also opened the JP1 for internal reference operation. However, I am still not getting the correct values and as Richard also said, I have to get the adc conversion error sorted out before I can even think of moving on to other issues.

Now if I try converting the adclo, I am getting reasonable results between 0 and 20 but if I try sampling 0.5v I am getting about 1500. I have carefully measured the output of the power supply as well as the adcin pin voltage and they are the same. I still don't know what is wrong!!!

David.

David,

Something is not adding up.  Let's try this:

1. Disconnect all bench equipment (voltage references, op-amps, etc) from your board; the only things connected should be the 5V DC supply on P6 and the USB cable for the embedded emulator
2. Depopulate JP1 ADCREFIN jumper
3. Jump JP1-1 (2.048V reference) directly to ADCINA2 on P9-6
4. Run an unmodified copy of the adc_soc example

You should be converting ~2796 on ADCINA2.

-Tommy

Thank you.

I have carried out the test as you told me to.... I removed all connections from the board except the power and usb cable, I depopulated JP1 then I jumped JP1-1 directly to ADCINA2. I observed about ~530. I measured the voltage from JP1-1 with respect to adclo, it was 2.048v as expected. Then I decided to carry out the same test for all other pins by changing conv00 from 0-15 for both boards. The results for the two ezdspf28335 boards are as follows:


BOARD 1

       ADCINA 0-7                            JP1-1                      ADCINB 0-7                             JP1-1
[506,504,510,513,510...]            2.048v       [2817,2817,2813,2812,2815...]       0.984v
[526,522,518,510,522...]            2.048v       [2542,2540,2538,2537,2544...]       0.994v
[538,534,518,540,522...]            2.048v       [2534,2534,2534,2540,2538...]       1.004v
[2655,2654,2653,2652,2650...]  1.007v       [2714,2718,2714,2718,2714...]       0.994v
[2614,2614,2616,2618,2621...]  1.015v       [474,466,466,458,484...]                 2.048v
[2714,2714,2715,2715,2718...]  1.020v       [2730,2733,2732,2734,2736...]       1.020v
[2788,2788,2787,2783,2783...]  1.032v       [2771,2769,2773,2769,2769...]       1.010v
[2817,2817,2813,2812,2815...]  1.040v       [2805,2805,2805,2804,2805...]       1.024v

BOARD 2

         ADCINA 0-7                                JP1-1               ADCINB 0-7                                     JP1-1
[522,530,534,530,538...]              2.046V        [2320,2320,2310,2311,2313...]      0.974V
[513,522,512,514,506...]              2.046V        [2199,2189,2187,2189,2195...]      0.984V
[541,550,544,546,546...]              2.046V        [2337,2334,2343,2337,2331...]      0.988V
[2716,2716,2714,2719,2715...]   1.000V         [2611,2612,2616,2614,2616...]      0.975V
[2614,2610,2620,2618,2612...]   1.010V         [466,473,470,470,470...]                2.046V
[2700,2690,2692,2697,2696...]   1.019V         [2637,2642,2637,2641,2634...]      1.006V
[2714,2722,2723,2715,2726...]   1.022V         [2674,2678,2682,2682,2682...]      1.002V
[2739,2736,2742,2741,2735...]   1.032V         [2714,2714,2714,2714,2714...]      1.020V

Although, the digital values are totally off key, I think there is some sort of pattern to it. I hope with this, we will be able see what's going on better.

What do you think?

Is there still hope for the boards?

Hope to hear from you soon.

David.

David,

 I think I saw you mention your using ccsv3.3 which is kind of old.

 There was mention in a real old post that there was a bug in the Example_2833xAdcSoc.c

You may wish to review the post.

https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/160912#596971

Thanks a lot.

I am aware of INL and I have taken precautions against that. Although in the example, it appears the ADCCLK is left at 25MHz due to

 EALLOW;
 SysCtrlRegs.HISPCP.all = ADC_MODCLK;     //ADC_MODCLK 0x3
 EDIS;

then I set my ADCCLKPS to 1 to reduce it to 12.5MHz. Yet I get [2751,2752,2749,2751,2749...] for 0.992v and that's the problem.

Plus, I only use ccs3v3 whenever I want to convert Simulink blocks to code but for the adc_soc example which is the code itself, I use ccsV6 directly.

David.

If you and using old example code,  it may not have the update.

another thread

https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/161012#593027

I get your point and I have checked the 2 threads (thanks by the way), I am positive that I am using the updated code so I don't think I should be experiencing any INL.
I feel there must be another problem.
David.

Thanks Tommy.

Yes my multimeter is >10Meg. I took the reading while the conversion was on and when I paused code (basically the same result).

I thought so too but the pins look pretty okay to me.

check it out.

Thanks Tommy.

I am already working towards getting another dsp chip. Hopefully, that'll be all I need. I will let you know how it goes.

Kind regards.

David.