TMS320F28377D: EMIF: order of accesses for narrower bus width than access width

Hi,

If I make 16-bit accesses via the EMIF address space will the access be divided into two 8-bit accesses? Where in the F28377D documentation is this stated?

Yes, 16bit access will be split into 2 8bit access. This is more of implementation detail hence not mentioned in the document.

My external device is 16-bit internally and requires that the 8-bit accesses via the bus are performed in a particular order (low address first). Is there a guaranteed order for the accesses made by the F28377D? Where in the F28377D documentation is this stated?

This requirement look a bit strange. External device should generate the byte enables based on the address decoding. What EMIF guarantees is the address and corresponding data is correct. Which means if 16bit write access (e.g. data 0xABCD) is performed at 16bit address 0x0 then EMIF will always give data 0xCD for byte address 0x0 and 0xAB for byte address 0x1. I need to check on the order with our design team and get back to you.

Regards,

Vivek Singh 

Hi Vivek,

Do you have any more details on the order of the EMIF accesses?

My reason for asking is that the external device has a 16-bit FIFO that must be written in the correct sequence (increment address) by the 8-bit writes for the data to be latched into the FIFO.

Thanks,

Iain

Iain,

Yes, lower byte will be written first and then upper byte.

Regards,

Vivek Singh