Tool/software: Code Composer Studio
Iam running Universal Parallel Port of microcontroller in receiver mode. A XILINX FPGA is running in transmit mode. <0.1% of bytes goes missing during UPP transfer.
UPP transmitter implementation in FPGA:
Clock frequency = 7.5MHz, Word length = 512 bytes, SDR mode, Enable is always made high, START is made high(for one clock cycle) at the start of 512 byte word.
START and DATA changes on pos edge of clock.
From timing diagram given it seems reasonable.
But following extract is from Technical reference manual of microcontroller:
"The uPP transmitter drives the CLOCK signal to align all other uPP signals. By default, other signals align on the rising edge of CLOCK, but its polarity is controlled by the CLKINVA bit in IFCFG register. The active edge(s) of CLOCK should always slightly precede transitions of other uPP signals."
This seems bit confusing. At what edge does microcontroller samples DATA and START?
Can the way that I implemented UPP transmitter, cause any timing issue?
