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TMS320F28069: When PWM2 was operated by adding a phase difference to PWM1, In a phase difference, the output of PWM2 periodically becomes a skip cycle. # 2

Part Number: TMS320F28069

Hi Kris-san,

There is an additional question for the resolved thread.
https://e2e.ti.com/support/microcontrollers/c2000/f/171/p/624205/2324116

【Question 1】
If EPwm2Regs.TBCTL.bit.PHSDIR = TB_UP is set, it seems to be (direction in which PWM2 moves toward PWM1).

 PWM2A = Low / PWM2B = High

→ When actually checking, there was no skip cycle.

From this, it seems that skip cycle will occur only when EPwm2Regs.TBCTL.bit.PHSDIR = TB_DOWN.


【Question 2】
When set to Up Mode or Down Mode, set TBPRD = 0x02C0E100 (set the same frequency as in UpdownMode).

· When TBPHS = 0x00000000 (no deviation),
 PWM2A = Low / PWM2B = High

· When TBPHS = 0x015FF000 (180 [deg] shift),
 PWM2A = High / PWM2B = Low remains

Or, it seems that it may not occur in Up Mode because skip cycle occurs only in Down Mode.
 → This is unconfirmed.

Is it a occur skip cycle only when Up-Down Mode and PHSDIR = TB_DOWN?
Even in other operation modes it is a phenomenon occurring depending on the SYNC signal and the rise / fall timing of PWM2?


In the sample project, it is for debugging that the TBPHS register is written at about 3 MHz cycle.
Normally, it is written at the depending timing of PWM update.

for (;;)
{
    GpioDataRegs.GPBTOGGLE.bit.GPIO 34 = 1;
    EALLOW;
    EPwm2Regs.TBPHS.all = uiDebug_TBPHS_ePWM2;
    EDIS;
}

Best regards,
Maekawa

  • Hi Maekawa,

    I'm not sure I understand the question(s). Was there a sample project that was supposed to be attached, or are you referring to the original post?

    Regards,
    Kris
  • Hi Kris-san,

    The problem of the previous thread is closed.

    This thread is a question you got from the customer based on the content you responded to in the previous thread.
    Please answer the following additional questions.

    Is it a occur skip cycle only when Up-Down Mode and PHSDIR = TB_DOWN?

    Or even other operation modes it is a phenomenon occurring depending on the SYNC signal and the rise / fall timing of PWM2?

    Best regards,
    Maekawa

  • Hi Kris-san,

    In the reply from the TIJ, at In up-down count mode: when counting up, 3 cycles after CTR = 0 until 3 cycles before CTR = PRD, and when counting down, 3 cycles after CTR = PRD until 3 cycles before CTR = 0.

    In my problem does not apply to this condition.
    Specifically, at the timing of SYNC_IN input, In the case of PWM2A falling or rising timing, It falls under the limit.
    That is, should it not work properly when the timing of change of CTR reload and HRPWM output is within ±3 clocks?

    Best regards,
    Maekawa

  • Hi Maekawa,

    The three cycle restriction is not tied to a specific TBCTR value. It is three cycles surrounding the events. So specifically in the case of a sync where TBPHSEN is set, it would be restricted for the 3 cycles following the sync. This is because the hardware is using those cycles to compute the HR values.

    Please let me know if this answered your question.

    Regards,
    Kris
  • Hi Maekawa,

    Since we have not heard back from you we hope that your issue is resolved. We are going to begin the process of closing the thread. If you have further questions, you may stop the process and post a response here.

    Thank you for choosing TI.

    Regards,
    Kris
  • Hi Kris-san,

    Thank you for reply.

    My customer have not yet resolved the problem, but we will close it as we understand the mechanism of occurrence.

    Best regards,
    Maekawa