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TMS320F28377D: CPU2 running RAM code loaded by CPU1

Part Number: TMS320F28377D

Hello,

I wonder if it is possible to load RAM code from CPU1 to CPU2 so it can run from there.

The target is to avoid having another .out file for CPU2.

The idea is to simplify the process when CPU2 has to run a small function, for example.

Regards,

Federico Rossi

  • it is possible, though not the direct method.
    you have to use the shared RAM and the routine has to be self contained so that it doesn't have references to other location which is not loaded in CPU2.

    How is this routine in cpu2 be triggered ? if it is through interrupt, then you need to setup interrupt vector table as well which will complicate things further.

    Regards
    Baskaran
  • Hello Baskaran.

    Thanks for the reply. I wonder how to trigger the routine.
    Suppose I have the main function (self-contained as you explained) in shared RAM at address A, loaded by CPU1 when it starts.
    How could I start CPU2 at address A?
    - Setting the program pointer of CPU2 from CPU1? Not sure if it is possible.
    - Does the CPU2 passes from a known shared RAM during the boot process where I could insert a branch to A?
    - Other way?

    Here is the context of my question:
    I would like to use this for a bootloader. The idea is to flash the bootloader only to CPU1, having only one .out file.
    When CPU1 start it load the flash api and the main function (A) to shared RAM. Then CPU2 starts running from A.
    CPU1 is able to program its flash but it is not able to program the CPU2 flash. If I understand only CPU2 can program its flash.
    When we want to program the CPU2 flash we send the data from CPU1 to CPU2 by IPC (not necessary using interrupts, it can be perform using IPC flags) so the main function (A) that runs in CPU2 can program its flash.
    Note that if CPU1 would be able to program CPU2 flash we would not need CPU2 at all for this application.
    BTW: If it is too complicated, having another .out in CPU2 would not be a big deal but I would like understand the process.

    Regards,
    Federico
  • Federico

    With CPU2 booting to idle, it has its IPCs enabled. Refer to the IPC commands in the TRM: http://www.ti.com/lit/spruhm8
    IPC branch call and function call can allow CPU2 to run the code in shared RAM. From there you can have CPU2 program its own flash.

    Best regards
    Chris