This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CCS/TMS320F28069: ISR service program stack time

Part Number: TMS320F28069

Tool/software: Code Composer Studio

Hi , I want to know the register push time when the ISR server   between  C28x  and CLA .

then i put a "EPwm5Regs.AQSFRC.bit.OTSFB = 1;" to test the time. but the result is different with what i know from the assembler.

the PWM sets 

EPwm5Regs.CMPA.half.CMPA = PRD_500k+1;
EPwm5Regs.CMPB = PRD_500k+1;

EPwm5Regs.AQCTLA.bit.ZRO = AQ_SET;
EPwm5Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm5Regs.AQCTLB.bit.ZRO = AQ_SET;
EPwm5Regs.AQCTLB.bit.CBU = AQ_CLEAR;

EPwm5Regs.AQSFRC.bit.ACTSFA = 1;
EPwm5Regs.AQSFRC.bit.ACTSFB = 1;
EPwm5Regs.AQSFRC.bit.RLDCSF = 3;

then I saw the C28 assembler as follow,

00a000: 761B ASP
00a001: FFF0 PUSH RB
00a002: ABBD MOVL *SP++, XT
00a003: A0BD MOVL *SP++, XAR5
00a004: C2BD MOVL *SP++, XAR6
00a005: C3BD MOVL *SP++, XAR7
00a006: E20000BD MOV32 *SP++, STF
00a008: E20300BD MOV32 *SP++, R0H
00a00a: E20301BD MOV32 *SP++, R1H
00a00c: E20302BD MOV32 *SP++, R2H
00a00e: E20303BD MOV32 *SP++, R3H
00a010: E6300600 SETFLG RNDF32=1,RNDF64=1
00a012: 2942 CLRC OVM|PAGE0
00a013: 5616 CLRC AMODE

 it just need 14 instruction sets and plus the "EPwm5Regs.AQSFRC.bit.OTSFB = 1;" with 8 instruction  are 22 sets totally.

but what i test is that  it need 36 sets.

And with CLA task takes 19 sets.

is there something wrong with my thought? or there are some instruction that CPU execute but i can't see it from the CCS debug windows. 

Thank you.

  • Can you clarify your question a little please?  How is the C code at the top related to the assembly code at the bottom?

    The assembly code looks like a context save, and it sounds like you are trying to measure the time to get into an ISR from an interrupt trigger (not shown).  Probably the discrepancy in your measurement is accounted for by the CPU auto-context save which takes 14 cycles (see attachment: 36 - 22 = 14), but I cannot be sure without knowing how you are triggering the interrupt.  Also, what you are measuring with the CLA?  Could you elaborate please?

    Thank you.

    Regards,

    Richard

    1351.C28x Interrupt Latency.pdf

  • Thanks for your reply! Richard
    I take the test as follow, the EPWM5 using count-up mode and the EPWM5B set high always(duty=1), the interrupt trigger is when count = zero then i put "EPwm5Regs.AQSFRC.bit.OTSFB = 1;" in the first line of ISR to test the interrupt latency .It takes 400ns(39cycles) . the assembly code above is copy from CCS debug window. so i confused if ISR just need to execute these assembly code(14 cycles) and the "EPwm5Regs.AQSFRC.bit.OTSFB = 1;"(8 cycles), the pulse time i expected should be 22cycles (244ns). but it takse 400ns. is there some instruction sets the CPU executed when ISR happen but i can't see from the CCS debug window? The same situation test when i ran in the CLA . I expected 8 cycles without interrupt latency . but it takes 19 cycles. Could you help me to figure out what wrong with my thoungt.
    Thank you.
  • I think i may understand C28 takes 36 cycles. i find this

    So when the CPU execute the ASP. The hardware excute 1-6 and it also takes time? And the time is about 14 cycles? 

  • No, the 14 cycles is accounted for in the diagram I sent with my last post.  It includes emptying the pipeline and the automatic context save (item 1 in the list).  The other hardware stuff happens in parallel.  If you're measuring 36 cycles, the remaining 22 are probably additional context save instructions inserted by the compiler.

    Attached is a list of registers protected by the hardware context save.  If you look at the assembly code in your first post, you'll see none of those registers are protected by hardware - the compiler is saving them.  The way you are measuring latency, you will be seeing these additional saves, together with a couple of cycles to set the OTSFB bit.

    There is no concept of an interrupt on the CLA, so I'm guessing you trigger a task from PWM5 which then sets the OTSFB bit.  You can set an MDEBUGSTOP instruction at the start of the task and then single step through the assembly to see what it's doing.  The CLA has an 8 stage pipeline which will have to be filled when the task commences.

    Regards,

    Richard 

    C2000 auto context save registers.pdf