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F28M35H52C: Details on VREFHI input

DO-Pro
Intellectual 610 points
Part Number: F28M35H52C

Hi,

In my Concerto-based design I plan to use an external reference so I'm looking for some additional information on VREFHI input of the A/D converter peripheral, namely, the spurious characteristics of external reference input. It's my understanding that for every conversion there will be a batch of 13 current spikes on that pin - one for Start of Conversion event followed by 12 spikes during conversion itself (one current spike per bit).  So here are my questions.

1. Are spikes in question follow with the ADC CLK frequency?

2. What is the magnitude and duration of these current spikes, worst case?

3. What's a max and min values of the switched weighted capacitors in the array used in that ADC?

4. What's a value of the on-resistance for analog switches used to switch weighted capacitors in the array?

5. What's a max settling time for voltages on weighted capacitors in the array during A/D conversion?

5. What's a max total value (including parasitics) of the VREFHI input capacitance that is seen by reference pin driver?

6. What are the static load requirements for the reference pin driver? The datasheet seems to provide the typical value of 100uA only but is totally mum on the possible maximum.

7. Is there any basic schematic detailing connectivity of the capacitive array to the reference pin that would help in simulating reference input circuit performance?

Please clarify these things for me.


Regards, Michael

  • 0
    TI__Guru 62975 points

    Michael,

    The ADC on F28M35H52C is not implemented as a true SAR architecture.  You should not expect to see periodic spikes in VREFHI inrush current during the conversion phase.  The reference voltage that is used by the ADC during conversion is a buffered version of the VREFHI input, which is why the ADC has an external reference trim field in the ADCREFTRIM register.

    I'll see if I can get some more background on the 100uA typical number, but my expectation is that it is a conservative value.

    -Tommy

  • 0 in reply to tlee
    Intellectual 610 points

    Tommy,

    Thank you for your quick response. So, based on your answer, do I understand it correctly that my reference driver won't see any spurious component from the conversion and will rather deal with nice and clean static current only that is specified as 100uA typical? Does it also mean that there is no need to add bulky storage capacitor on VREFHI pin? Should I then care about load transient response of the driver at all?

    Please confirm or disprove.

    And yet another question - based on TI's classification, what is the type of the ADC used on Concerto devices? It's certainly not a Type 3 as it is on classic 2808 part but which one?

    Regards, Michael

  • 0 in reply to DO-Pro
    TI__Guru 62975 points

    Michael,

    Correct, the ADC was designed to have very minimal requirements for the VREFHI source.  There is no hard requirement to have a bulk capacitor on the VREFHI pin.  Is there a reason for not using the internal VREFHI reference?

    The ADC on Concerto has the same implementation as the ADCs on F2802x, F2803x, F2805x, and F2806x.  You can reference this peripherals guide for more information.

    -Tommy

  • 0 in reply to tlee
    Intellectual 610 points

    Tommy,

    Thank you for proofing that. It then resolves my issue.

    Well, I'm a big fan of internal reference but yes, we do have a couple of reasons. First, it's not an entirely new design but rather an upgrade so we have to provide backward compatibility with existing applications. All of them have 0...3V analog signal outputs so we can't take advantage of expanded dynamic range with internal reference. We also have to minimize problems associated with porting existing code onto Concerto platform. Also potential re-certification concerns...

    BTW, is there any added advantage of using external reference with Concerto device accuracy-wise, etc? Will internal reference degrade system performance compared to externals?

    Thanks, Michael

  • 0 in reply to DO-Pro
    TI__Guru 62975 points

    Michael,

    Yes, the ADC will have more gain error when using the internal reference:

    This is really because the errors introduced by the internal reference are included in the +/- 60 LSB gain error.  The external reference is assumed to be perfect in the +/- 40 LSB gain error spec.

    -Tommy

  • 0 in reply to tlee
    Intellectual 610 points

    Thanks, Tommy.

    Have you had a chance to find out more regarding 100uA typical spec for VREFHI input current? Is it truly conservative value or should I budget for perhaps 1mA or higher as a worst case?

    Regards, Michael

  • 0 in reply to DO-Pro
    TI__Guru 62975 points
    Michael,

    I have not found the raw analysis yet, but my sense is that an extra 20% margin would put you in a very safe state.

    -Tommy
  • 0 in reply to tlee
    Intellectual 610 points

    Thank you, Tommy.

    And eventually my last thing for now. There is a possibility that during power-up an external reference voltage on VREFHI pins will rise somewhat faster than power rail. It might lead to the situation that VREFHI briefly, for 5-10ms, exceeds power rails of the Concerto device by up to 1V.

    Are VREFHI pins protected from overvoltage condition by clamping diodes and if yes, to which rails are these diodes connected?

    Are short time excursions similar to those described above acceptable at all, especially as far as reliable start-up and following code execution are concerned?

    I realize that it's generally not recommended and should be avoided but lack of board real estate causes some physical constraints and I have to set my priorities. Please clarify this moment for me.

    Regards, Michael

  • 0 in reply to DO-Pro
    TI__Guru 62975 points

    Michael,

    As you have stated, this is generally not recommended because of the risk of damage to the ESD diodes and the risk of latch-up.  Our standard advice is to use an external Shottky diode to shunt the extra voltage to the power supply.

    The VREFHI pin has ESD diode protection that can shunt excess energy to VDDA, but it does not support more than 2mA of continuous current.  Given the short exposure and relatively weak VREFHI source (<2mA), I think you will be ok with respect to ESD diode damage.

    For the risk of latch-up, the standard recommendation is to keep the VREFHI voltage lower than VDDA + 0.3V.  The risk increases as VREFHI exceeds VDDA + 0.3v, but you would probably be ok up to VDDA + 0.7V.  The ESD diode might be able to maintain this, but there's no way to know for sure until you try it.  I would consider this to be a relatively low risk, but I can't make any guarantees.

    -Tommy

  • 0 in reply to tlee
    Intellectual 610 points

    Thank you, Tommy.
    I have no further questions.

    Michael