TMS320F28379D: EMIF timings seen from component output

Clément Letonnelier said:

The first question relates to the Table 5-38, it is stated below the table that the minimum value for the parameters such as TA, RS, RST, ... is 1 while it is possible to write 1 in the corresponding fields of the ASYNC_CS*_CR registers.

You confirm that the minimum value of 1 in fact corresponds to the case when the field of the register is set to 0 (as value is a number of cycles minus one) ?

The Footnote (1) values for TA, RS, RST, RH, WS, WST, WH, and MEWC from the datasheet are given in terms of EMIF clock cycles.  What is programmed into the EMIF configuration registers will be one integer value less.

For example, the minimum RST value from the datasheet is 4 cycles, so the minimum EMIF[R_STROBE] register value would be 3.

You can also consider using the EMIF Configuration Tool that is described in the EMIF Application Note.

Clément Letonnelier said:

The second question is globally related to the timings provided in the tables from section 5.9.9.3.1 of the datasheet.

Are those timing "all inclusive" ?

I mean should we only take the EMIF section timings when doing our timing analysis or should we also:

• Add the rise and fall times of the GPO as provided in section 5.9.6.1 for output signals
• Add a SYSCLK period cycle for input signal, ie. the sampling period when QUALPRD is equal to 0 (which will be the case if we configure the GPIO as being an EMIF signal)

The GPIO characteristics do not need to be considered.   The 5.9.9.3.1 values are inclusive of input and output transitions.  The EMIF pins should have the associated GPIO QSEL settings configured to ASYNC (no qualification).  

Hello,

Thank you for your answer.

Wrt the second question, I am a bit suprise as I had a different answer some month ago from the TI Field Application engineer we have as contact.

Also, what can you tell me the output load that was used to test all the EMIF timings ?

I mean is it the same 40pF value than stated for the GPIO timings ? Without serial resistor or transmission line ?

I am asking this as we want to perform signal integrity analysis and compute compensation/flight time based on the effective load so we need to perform the genuine simulations with the test load.

Thanks,

Clément

Hello,

Any update on this topic ?

I am really kooking forward to getting an answer there on both the new questions and my surprise on the fact that I had different answers from two TI representatives.

Thank you,

Clément

Clément Letonnelier said:

Wrt the second question, I am a bit suprise as I had a different answer some month ago from the TI Field Application engineer we have as contact.

The maximum output transition time of the EMIF pins with 40pF load will satisfy the values provided in the GPIO switching characteristics table, so it does apply in a strict sense.  When considering the EMIF timing characteristics, the transition time to VOL/VOH should already be included in the values so you should not need to add any additional time for signal transition.

Clément Letonnelier said:

Also, what can you tell me the output load that was used to test all the EMIF timings ?

I mean is it the same 40pF value than stated for the GPIO timings ? Without serial resistor or transmission line ?

The EMIF timings were closed with the assumption that multiple memories would be connected to the interface.  It will take a few days to find the details.

Hi tlee,

Thank you for your answer.

If you could please provide me with the effective load considered for the EMIF timings that would be appreciated.

Especially as you state that the timings have most certainly be tested with multiple memories assumption, this could lead to the 40pF value in some conditions and you seem to say that in this case the GPIO timings should be taken into account.

And moreover, we are working in the aeronautical field so we need to justify everything you know :)

Thank you,
Clément

Tommy,

Perfect, thank you very much.

Clément